[AK1541]
Setup example
DITH = D14 in <Address3> is set to 1:
Available
Unavailable
VCO frequency
at the lower limit
[REFIN] pin input
frequency
180MHz
70MHz
12.8MHz
0
32MHz
2
{LDCKSEL[1:0]}
Formula
180MHz > 12.8/(0+1) x 7 = 89.6MHz
70MHz < 32/(2+1) x 7 = 74.67MHz
DITH = D14 in <Address3> is set to 0:
Available
Unavailable
60MHz
VCO frequency
180MHz
at the lower limit
[REFIN] pin input
12.8MHz
frequency
32MHz
{LDCKSEL[1:0]}
Formula
0
1
180MHz > 12.8/(0+1) x 4 = 51.2MHz
60MHz < 32/(1+1) x 4 = 64MHz
LDCKSEL=0
Ｔ
Reference clock
PFD clock
VCO divide clock
Phase detector output
Valid
Invalid
Invalid
Valid
Valid
Invalid
Valid
Lock detect result
Fig. 8 Digital Lock Detect Operation
MS1043-E-05
16
2013/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
