[AK1541]
4.2 Digital Lock Detect
The accuracy of the phase detect is set by {LDCKSEL[1:0]}.
{LDCKSEL[1:0]} is set to 0: T = REFIN cycle
{LDCKSEL[1:0]} is set to 1: T = REFIN cycle × 2 (This cannot be used for the reference dividing ratio ≤ 5.)
{LDCKSEL[1:0]} is set to 2: T = REFIN cycle × 3 (This cannot be used for the reference dividing ratio ≤ 6.)
In the digital lock detect, the [LD] pin outputs is ”Low” every time when the frequency is set. And the [LD] pin outputs is
“High” (which means the locked state) when a phase error smaller than T is detected for 63 times consecutively. If the
phase error is larger than T is detected for N times consecutively then the [LD] pin outputs is “High” and then the [LD] pin
outputs is “Low”(which means the unlocked state).
Since the AK1541 is a Delta-Sigma Fractional-N type, a phase error up to 7 times larger than the VCO period frequency
may occur in the phase detector. Therefore the {LDCKSEL[1:0]} setting should be large enough to cover the amplitude
of the Delta-Sigma Fractional frequency. However, if the VCO frequency does not satisfy either of the following formula,
the digital lock detect cannot be used. In such case, the analog lock detect should be used.
{DITH} = D14 in <Address3> is set to 1: VCO frequency > [REFIN] pin input frequency / [{LDCKSEL[1:0]} setting + 1] x 7
{DITH}= D14 in <Address3> is set to 0: VCO frequency > [REFIN] pin input frequency / [{LDCKSEL[1:0]} setting + 1] x 4
Example 1)
If [REFIN] pin input frequency = 33.6MHz, {DITH} = 1, {LDCKSEL[1:0]} = 2,
33.6MHz / (2+1) x 7 = 78.4MHz
As a result, the digital lock detect cannot be used if the VCO frequency is equivalent to or smaller than 78.4MHz.
Example 2)
If [REFIN] pin input frequency = 33.6MHz, {DITH} = 0, {LDCKSEL[1:0]}= 1,
33.6MHz / (1+1) x 4 = 67.2MHz
As a result, the digital lock detect cannot be used if the VCO frequency is equivalent to or smaller than 67.2MHz.
MS1043-E-05
15
2013/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
