Series AMLD-Z
Up to 1000mA | LED Driver
Output Current Adjustment by PWM Control:
Driving VADJ Directly
A Pulse Width Modulation (PWM) signal with a duty cycle DPWM can be applied to the ADJ pin as shown below.
The output current is given by:
[if PWM frequency < 300Hz,
for 0.1<DPWM<1]
Iout ≈
Ioutnom x DPWM
+Vout
1st LED
1
PWM
VADJ
AMLD-Z
-Vin
1.25V
0V
-Vout
Last LED
1
GND
Driving VADJ Via Open Collector Transistor
The VADJ can also be driven via an open collector transistor as shown below.
The diode and resistor serve to suppress any possible high amplitude negative voltage spikes to the VADJ input resulting
from the collector to emitter capacitance of the transistor. Any negative voltage spikes will cause errors in output current
and/or unstable driver operation.
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