Appendix B: PCB Layout Suggestion
The HSDL 3209 is a shieldless
part and hence does not
contain a shield trace unlike
the other transceivers. The
following PCB layout
guidelines should be followed
to obtain a good PSRR and EM
immunity resulting in good
electrical performance. Things
to note:
Top layer
Connect the metal shield & module
ground pin to bottom ground layer
Layer 2
Critical ground plane zone. Do not connect
directly to the module ground pin
Layer 3
Keep data bus away from critical ground
plane zone
1. The ground plane should be
continuous under the part.
Bottom layer
(GND)
2. VLED can be connected to
either unfiltered or
unregulated power supply. If
VLED and Vcc share the
same power supply, CX3
need not be used and the
connections for CX1 and
CX2 should be before the
current limiting resistor R1.
CX1 is generally a ceramic
capacitor of low inductance
providing a wide frequency
response while CX2 and
CX3 are tantalum capacitors
of big volume and fast
The area underneath the
module at the second layer,
and 3cm in all direction
around the module is defined
as the critical ground plane
zone. The ground plane should
be maximized in this zone.
Refer to application note
AN1114 or the Agilent IrDA
Data Link Design Guide for
details. The layout below is
based on a 2-layer PCB.
frequency response. The use
of a tantalum capacitor is
more critical on the VLED
line, which carries a high
current. CX4 is an optional
ceramic capacitor, similar to
CX1, for the IOVcc line.
3. Preferably a multi-layered
board should be used to
provide sufficient ground
plane. Use the layer
Bottom View
Top View
underneath and near the
transceiver module as Vcc,
and sandwich that layer
between ground connected
board layers. Refer to the
diagram below for an
example of a 4 layer board,
12
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