If the clear input (CLR) equals
zero for one internal display cycle
(4 ms minimum), the data in the
ASCII RAM will be rewritten with
zeroes and the display will be
blanked. Note that the blanking
input (BL) must be equal to
logical one during this time.
Data Entry HPDL-2416
Figure 4 shows a truth table for
the HPDL-2416 display. Setting
the chip enables (CE
1
, CE
2
) to
their low state and the cursor
select (CU) to its high state will
enable data loading. The desired
data inputs (D
6
-D
0
) and address
inputs (A
1
, A
0
) as well as the chip
enables (CE
1
, CE
2
) and cursor
select (CU) must be held stable
during the write cycle to ensure
that the correct data is stored
into the display. Valid ASCII data
codes are shown in Figure 1. The
display accepts standard seven-
bit ASCII data. Note that D
6
≠
D
5
for the codes shown in Figure 4.
If D
6
= D
5
during the write cycle,
then a blank will be stored in the
display. Data can be loaded into
the display in any order. Note
that when A
1
= A
0
= 0, data is
stored in the furthest right-hand
display location.
Cursor Entry HPDL-2416
As shown in Figure 4, setting the
chip enables (CE
1
, CE
2
) to their
low state and the cursor select
(CU) to its low state will enable
cursor loading. The cursor
character is indicated by the
display symbol having all 16
segments and the DP ON. The
least significant data input (D
0
),
the address inputs (A
1
, A
0
), the
chip enables (CE
1
, CE
2
), and the
cursor select (CU) must be held
stable during the write cycle to
Figure 2. HPDL-1414 Write Truth Table.
Display Internal Block
Diagram HPDL-2416
Figure 3 shows the internal block
diagram for the HPDL-2416
display. The CMOS IC consists of
a four-word ASCII memory, a
four-word cursor memory, a
64-word character generator, 17
segment drivers, four digit
drivers, and the scanning circuitry
necessary to multiplex the four
monolithic LED characters. In
normal operation, the divide-by-
four counter sequentially
accesses each of the four RAM
locations and simultaneously
enables the appropriate display
digit driver. The output of the
RAM is decoded by the character
generator which, in turn, enables
the appropriate display segment
drivers. For each display location,
the cursor enable (CUE) selects
whether the data from the ASCII
RAM (CUE = 0) or the stored
cursor (CUE = 1) is to be
displayed. The cursor character is
denoted by all sixteen segments
and the DP ON. Seven-bit ASCII
data is stored in RAM. Since the
display utilizes a 64-character
decoder, half of the possible 128
input combinations are invalid.
For each display location where
D
5
= D
6
in the ASCII RAM, the
display character is blanked. The
entire display is blanked when
BL = 0.
Data is loaded into the display
through the data inputs (D
6
- D
0
),
address inputs (A
1
, A
0
), chip
enables (CE
1
, CE
2
), cursor select
(CU), and write (WR). The cursor
select (CU) determines whether
data is stored in the ASCII RAM
(CU = 1) or cursor memory
(CU = 0). When CE
1
= CE
2
=
WR = 0 and CU = 1, the informa-
tion on the data inputs is stored
in the ASCII RAM at the location
specified by the address inputs
(A
1
, A
0
). When CE
1
= CE
2
= WR
= 0 and CU = 0, information on
the data input, D
0
, is stored in the
cursor at the location specified by
the address inputs (A
1
, A
0
). If D
0
= 1, a cursor character is stored
in the cursor memory. If D
0
= 0,
a previously stored cursor
character will be removed from
the cursor memory.
3-182
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
