Electrical Description
Display Internal Block
Diagram HPDL-1414
Figure 1 shows the internal block
diagram of the HPDL-1414. It
consists of two parts: the display
LEDs and the CMOS IC. The
CMOS IC consists of a four-word
ASCII memory, a 64-word charac-
ter generator, 17 segment drivers,
four digit drivers, and the
scanning circuitry necessary to
multiplex the four monolithic
LED characters. In normal
operation, the divide-by-four
counter sequentially accesses
each of the four RAM locations
and simultaneously enables the
appropriate display digit driver.
The output of the RAM is decoded
by the character generator which,
in turn, enables the appropriate
display segment drivers. Seven-
bit ASCII data is stored in RAM.
Since the display uses a 64-
character decoder, half of the
possible 128 input combinations
are invalid. For each display
location where D
5
= D
6
in the
ASCII RAM, the display character
is blanked.
Data Entry HPDL-1414
Figure 2 shows a truth table for
the HPDL-1414. Data is loaded
into the display through the
DATA inputs (D
6
-D
0
), ADDRESS
inputs (A
1
-A
0
), and WRITE (WR).
After a character has been
written to memory, the IC
decodes the ASCII data, drives
the display and refreshes it
without any external hardware or
software.
Figure 1. HPDL-1414 Internal Block Diagram.
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AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
