9
Electrical Description
Pin Function
RESET (RST, pin 1)
FLASH (FL, pin 2)
ADDRESS INPUTS
(A
0
-A
4
, pins 3-6, 10)
Description
Initializes the display.
FL low indicates an access to the Flash RAM and is unaffected by the
state of address lines A
3
-A
4
.
Each location in memory has a distinct address. Address inputs (A
0
-A
2
)
select a specific location in the Character RAM, the Flash RAM or a
particular row in the UDC (User-Defined Character) RAM. A
3
-A
4
are
used to select which section of memory is accessed. Table 1 shows the
logic levels needed to access each section of memory.
Table 1. Logic Levels to Access Memory
Section of Memory
Flash RAM
UDC Address Register
UDC RAM
Control Word Register
Character RAM
CLOCK SELECT
(CLS, pin 11)
CLOCK INPUT/OUTPUT
(CLK, pin 12)
WRITE (WR, pin 13)
CHIP ENABLE (CE, pin 17)
READ (RD, pin 18)
DATA Bus (D
0
-D
7
,
pins 19, 20, 23-28)
GND (SUPPLY) (pin 15)
GND (LOGIC) (pin 16)
V
DD
(POWER) (pin 14)
FL
0
1
1
1
1
A
4
X
0
0
1
1
A
3
X
0
1
0
1
A
2
A
1
A
0
Char. Address
Don't Care
Row Address
Don’t Care
Character Address
Used to select either an internal (CLS = 1) or external (CLS = 0) clock source.
Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave
displays.
Data is written into the display when the WR input is low and the
CE input is low.
Must be at a logic low to read or write data to the display and must go
high between each read and write cycle.
Data is read from the display when the RD input is low and the CE
input is low.
Used to read from or write to the display.
Analog ground for the LED drivers.
Digital ground for internal logic.
Positive power supply input.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
