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HDSP-2111 参数 Datasheet PDF下载

HDSP-2111图片预览
型号: HDSP-2111
PDF下载: 下载PDF文件 查看货源
内容描述: 八字符5毫米和7毫米智能字母数字显示器 [Eight Character 5 mm and 7 mm Smart Alphanumeric Displays]
分类和应用: 显示器光电
文件页数/大小: 16 页 / 408 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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6
Optical Characteristics at 25
°
C
[1]
V
DD
= 5.0 V at Full Brightness
Part
Number
HDSP-2107
-2504
HDSP-2112
-2502
HDSP-2110
-2500
HDSP-2111
-2501
HDSP-2113
-2503
Luminous Intensity
Character Average (#)
Iv (mcd)
Min.
Typ.
5.0
15.0
2.5
2.5
2.5
2.5
7.5
7.5
7.5
7.5
Peak
Wavelength
λ
Peak
(nm)
645
635
600
583
568
Dominant
Wavelength
λ
d
(nm)
637
626
602
585
574
Description
AlGaAs
HER
Orange
Yellow
High
Performance
Green
Note:
1. Refers to the initial case temperature of the device immediately prior to measurement.
AC Timing Characteristics Over Temperature Range (-45
°
C to +85
°
C)
4.5 V < V
DD
< 5.5 V, unless otherwise specified
Reference
Number
1
Symbol
t
ACC
t
ACS
t
CE
t
ACH
t
CER
t
CES
t
CEH
t
W
t
WSU
t
WH
t
R
t
RD
t
DF
t
RC
Description
Display Access Time
Write
Read
Address Setup Time to Chip Enable
Chip Enable Active Time
[2,3]
Write
Read
Address Hold Time to Chip Enable
Chip Enable Recovery Time
Chip Enable Active Prior to Rising Edge of
[2,3]
Write
Read
Chip Enable Hold Time to Rising Edge of
Read/Write Signal
[2,3]
Write Active Time
Data Write Setup Time
Data Write Hold Time
Chip Enable Active Prior to Valid Data
Read Active Prior to Valid Data
Read Data Float Delay
Reset Active Time
[4]
Min.
[1]
210
230
10
140
160
20
60
140
160
0
100
50
20
160
75
10
300
Units
2
3
ns
ns
4
5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
9
10
11
12
13
Notes:
1. Worst case values occur at an IC junction temperature of 150° C.
2. For designers who do not need to read from the display, the Read line can be tied to V
DD
and the Write and Chip Enable lines can be
tied together.
3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM,
regardless of the logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110
µs
min. using the internal refresh clock) after the rising edge of the
reset line.