4
RELATIVE GAIN – dB
-LCK_REF
0
1
1
1
1
EWRAP
x
0
0
1
1
LUNUSE
x
0
1
1
0
Rx Lock
CLKIN
DI
CLKIN
LI
LI
2
0
-2
-4
-6
-8
The table above llustrates these
various settings.
Normally, the recovered serial
clock is used by the clock gener-
ator to generate the various
internal clocks the receiver uses
including the receive clock
outputs RBC0 (pin 69) and RBC1
(pin 67).
The final receiver clocking
feature is included for test
purposes only. By applying a low
to the -TCLKSEL input, pin 5, the
internal phase locked loop is
bypassed and the receiver uses
the CLKIN signal as the high
speed serial clock. Under normal
operating conditions the
-TCLKSEL pin should be tied
high.
In a Fibre Channel link, frame
alignment is accomplished
through the transmission and
detection of the special character
K28.5, also known as a comma
character. Prior to actual data
transmission the system will
transmit a comma character over
the physical link. To start, the
receiver should be frequency
locked to the local reference
oscillator (-LCKREF set low). To
ensure frequency lock is
achieved, -LCKREF should be
held low for a minimum of 500
µsec
(see Rx Timing Characteris-
tics, t
flock
). It then should be
toggled high. At this point the
receiver will phase lock to the
662
incoming data stream at the
±
DI
input but the actual frame or
word boundary will be undeter-
mined. The EN_CDET pin (# 38)
should be set high now. With the
EN_CDET pin set high, the
receiver will scan the incoming
data stream for a comma charac-
ter. Once a comma character is
received, the internal clocks and
registers are reset giving proper
frame alignment. The receiver
will reset on every comma
character that is transmitted as
long as EN_CDET is held high.
When the internal clock genera-
tor is reset due to the detection of
a comma character, internal
circuitry prevents a clock “sliver”
from appearing at the receive
clock outputs (RBC0 and RBC1).
This antisliver circuit assures
each clock output high, or low,
will be held for at least one half
the frame rate time. When
EN_CDET is set low the receiver
ignores all incoming comma
characters and assumes the
current frame and bit alignment
is correct. EN_CDET is
automatically disabled when
-LCKREF is set low. The
COM_DET pin, #75, on the
receiver will go high when a
comma character is detected (see
Figure 15).
Now that frame alignment has
been achieved, the receiver is
ready to receive full speed serial
data and demultiplex it back to
its original 10 bit or 20 bit
-10
1.00E
+ 06
1.00E
+ 07
1.00E
+ 08
1.00E
+ 09
1.00E
+ 10
FREQUENCY – f – Hz
Figure 7. Typical Frequency Response
Plot of the Internal Input Equalizer.
parallel word format. This data is
then placed into the output latch.
The data output is presented in
the standard TTL output levels
and characteristics specified in
the dc and ac Electrical Specifica-
tion tables. When operating in
531 Mbaud mode the receiver
generates output data in a single
byte wide (10 bits) output format.
This is data byte 0 and is denoted
RX[00:09] on pins 53 through
62. In 1063 Mbaud mode the data
output is generated in a two byte
wide (20 bits) format, data byte 0
and data byte 1. Data byte 0 is
denoted RX[00:09] on pins 53
through 62 and data byte 1 is
denoted RX[10:19] on pins 43
through 52. In standard operation
data byte 0 and data byte 1 will
both be clocked into the output
latch at the same time, on the
falling edge of RBC0. An
alternate mode of operation is
ping-pong mode. In ping-pong
mode the data is clocked out 1
byte at a time with byte 0 clocked
out on the falling edge of RBC0
and byte 1 clocked out on the
falling edge of RBC1. To set the
receiver to operate in ping-pong
mode, the PPSEL pin, # 76,
should be set high (otherwise it
should be tied low).
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
