Interfacing the HCTL-
20XX to an Intel 8748
is the crystal frequency divided
by 3. T0 must be enabled by
executing the ENT0 CLK
instruction after each system
reset, but prior to the first
encoder position change. An
8748 program which interfaces
to the circuit in Figure 17 is
given in Figure 18. The resulting
interface timing is shown in
Figure 19.
The circuit shown in Figure 17
shows the connections between
an HCTL-20XX and an 8748.
Data lines D0-D7 are connected
to the 8748 bus port. Bits 0 and 1
of port 1 are used to control the
OE and SEL inputs of the HCTL-
20XX respectively. T0 is used to
provide a clock signal to the
HCTL-20XX. The frequency of T0
* NOTE: PIN NUMBERS ARE DIFFERENT FOR THE HCTL-2020.
Figure 17. An HCTL-20XX-to-Intel 8748 Interface.
Object
LOC Code
Source
Statements
Comments
000
99 00
ANL P1, 00H Enable output and higher order
bits
002
003
004
08
INS A, BUS
MOVE R0, A
Load higher order bits into ACC
Move data to register 0
A8
89 02
ORL P1, 02H Enable output and lower order
bits
006
008
009
00B
08
INS A, BUS
MOV R1, A
Load order bits into AC
Move data to register 1
A9
89 03
93
ORL P1, 03H Disable outputs
RETR Return
Figure 18. A Typical Program for Reading HCTL-20XX with an 8748.
2-194
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
