In this circuit an interface to a
Motorola 6802/8 and a cascading
scheme for a 24-bit counter are
shown. This circuit provides a
minimum part count by: 1) using
two 74LS697 Up/Down counters
with output registers and tri-state
outputs and 2) using a Motorola
6802/8 LDX instruction which
stores 16 bits of data into the
used to clock the HCTL-2020.
Address AO is connected directly
to the SEL pin on the HCTL-
2020. This line selects the low or
high byte of data from the HCTL-
2020.
a single double-byte fetch
instruction (LDX 2XX0). This
instruction is a five cycle
instruction which reads external
memory location 2XX0 and stores
the high order byte into the high
byte of the index register.
Memory location 2XX1 is next
read and stored in the low order
byte of the index register. The
high byte of counter data is
clocked into the 74LS697
registers when SEL is low and
OE goes low. This upper byte can
be read at any time by pulling the
74LS697 G low when reading
address 4XXX. Figure 15 shows
memory addresses and gives an
example of reading the HCTL-
2020. Figure 16 shows the
Cascading is accomplished by
connecting the CNT
output on
CAS
the HCTL-2020 with the counter
index registers in two consecutive clock (CCK) input on both
clock cycles.
74LS697s. The U/D pin on the
HCTL-2020 and the U/D pin on
both 74LS697s are also directly
connected for easy expansion.
The RCO of the first 4-bit
74LS697 is connected to the ENT
pin of the second 74LS697. This
enables the second counter only
when there is a RCO signal on the
first counter.
The HCTL-2020 OE and the
74LS697 G lines are decoded
from Address lines A15-A13. This
results in counter data being
enabled onto the bus whenever
an external memory access is
made to locations 4XXX or 2XXX.
Address line A12 and processor
clock E enables the 74LS138.
The processor clock E is also
interface timing for the circuit.
This configuration allows the
6802 to read both data bytes with
Address
Function
CXXX
4XXX
2XX0
2XX1
Reset Counters
Enable High Byte on Data Lines
Enable Mid Byte on Data Lines
Enable Low Byte on Data Lines
Read Example
LDX 2000
STX 0100
Loads mid byte and then low byte into
memory locations 0100 and 0101
LDAA 4000
STAA 0102
Loads the high byte into memory
location 0102
Figure 15. Memory Addresses and Read Example.
2-192
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
