ANL P1, OOH
ORL P1, 02H
Figure 19. 8748 READ Cycle from Figure 18.
Actions
Additional Information
from Hewlett-Packard
Application briefs are available
from the factory. Please contact
your local HP sales representative
for the following.
M027 Interfacing the HCTL-20XX
to the 8051
M019 Commonly Asked
Questions about the HCTL-
2020 and Answers
M020 A Simple Interface for the
HCTL-2020 with a 16-bit
DAC without Using a
Processor
M023 Interfacing the MC68HCII
to the HCTL-2020
20XX detects OE is low and
SEL is high on the next falling
edge of the CLK, and thus the
first inhibit reset condition is
met.
1. ANL P1, 00H has just been
executed. The output of bits 0
and 1 of Port 1 cause SEL and
OE to be logic low. The data
lines output the higher order
byte.
5. INS A, BUS has just been
executed. Lower order data
bits are read into the 8748.
6. ORL P1, 03H has just been
executed. The HCTL-20XX
detects OE high on the next
falling edge of CLK. The
2. The HCTL-20XX detects that
OE and SEL are low on the
next falling edge of the CLK
and asserts the internal inhibit
signal. Data can be read
without regard for the phase of
the CLK.
3. INS A, BUS has just been
executed. Data is read into the
8748.
4. ORL PORT 1, 02H has just
been executed. The program
sets SEL high and leaves OE
low by writing the correct
values to port 1. The HCTL-
program sets OE and SEL high
by writing the correct values to
port 1. This causes the data
lines to be tristated. This
satisfies the second inhibit and
reset condition. On the next
rising CLK edge new data is
transferred from the counter to
the position data latch.
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