HCTL-2020
INTERNAL CLOCK
FFFF 0000
CLK
SEL
OE
INTERNAL
INHIBIT
CNT
CAS
RCK
G
DATA
BUS
HIGH Z
MID
BYTE
LOW
BYTE
HIGH
BYTE
1
1
1
4
5
7
8
9
10
ACTIONS
2
3
6
Figure 16. Interface Timing for the 6802/8.
Actions
has occurred and OE has
been pulled low to start a
read cycle. SEL and OE are
gated to give RCK which
latches the external high
byte, equal to 00H. The
falling edge, of the CNTCAS
signal counts up the
6. With the first negative edge
after OE and SEL go high,
the first of the two HCTL-
2020 inhibit reset conditions
is met and the 6802 reads
the low byte in.
7. The data bus returns to the
high impedance state, when
OE goes high.
8. With the first negative edge
of the clock after OE goes
high, inhibit reset is
complete.
9. With the positive going edge
of the clock, G is asserted
and the external high byte,
00H is available on the data
bus from 9 through 10 and
the 6802 reads the high byte
in at (10).
1. The microprocessor clock
output is E. If the internal
HCTL-2020 inhibit is not
active, new data is trans-
ferred from the internal
counter to the position data
latch.
2. An even address output
from the 6802 causes SEL to
go low. When E goes high,
the address decoder output
for the HCTL-2020 OE
external counter to 0001H.
3. With the first negative edge
of the clock after SEL and
OE are low the internal
latches are inhibited from
counting and the 6802 reads
the high byte in.
signal goes low. This causes
the HCTL-2020 to output
the middle byte of the
system counter (high byte of
the HCTL-2020 counter).
This middle byte, FFFFH is
available at (2) through (4),
the first time OE is low. In
this example an overflow
4. OE goes high and the data
bus goes into a high
impedance state.
5. OE is low and SEL is high
and the low byte is enabled
onto the data bus. The low
byte is valid through (7).
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AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
