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HCPL0454 参数 Datasheet PDF下载

HCPL0454图片预览
型号: HCPL0454
PDF下载: 下载PDF文件 查看货源
内容描述: 高CMR ,高速光电耦合器 [High CMR, High Speed Optocouplers]
分类和应用: 光电
文件页数/大小: 17 页 / 232 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Package Characteristics
Over recommended temperature (T
A
= 0°C to 25°C) unless otherwise specified.
Parameter
Input-Output
Momentary
Withstand
Voltage†
Input-Output
Resistance
Sym.
V
ISO
Device
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
(Option 020)
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
Min.
2500
5000
5000
10
12
10
12
10
11
10
13
0.6
0.5
0.6
pF
V
I-O
= 500 Vdc
T
A
= 25°C
T
A
= 100°C
f = 1 MHz
Typ.*
Max.
Units
V rms
Test Conditions
RH
50%,
t = 1 min.,
T
A
= 25°C
Fig.
Note
6, 13
6, 14
6, 11,
14
6
R
I-O
Input-Output
Capacitance
C
I-O
6
*All
typicals at T
A
= 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, I
O
, to the forward LED input current,
I
F
, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive)
dV
CM
/dt on the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a Logic High state
(i.e., V
O
> 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dV
CM
/dt on the
trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a Logic Low state (i.e., V
O
< 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is
the maximum tolerable dV
CM
/dt on the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a
Logic High state (i.e., V
O
> 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dV
CM
/dt on
the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a Logic Low state
(i.e., V
O
< 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The R
L
= 20 kΩ, C
L
= 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1
µF
bypass capacitor connected between pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
3000 V rms for 1 second
(leakage detection current limit, I
i-o
5
µA).
This test is performed before the 100% Production test shown in the VDE 0884
Insulation Related Characteristics Table, if applicable.
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
6000 V rms for 1 second
(leakage detection current limit, I
i-o
5
µA).
This test is performed before the 100% Production test shown in the VDE 0884
Insulation Related Characteristics Table, if applicable.
15. The difference between t
PLH
and t
PHL
between any two devices (same part number) under the same test condition. (See Power
Inverter Dead Time and Propagation Delay Specifications section.)
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