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HCPL-9031 参数 Datasheet PDF下载

HCPL-9031图片预览
型号: HCPL-9031
PDF下载: 下载PDF文件 查看货源
内容描述: 高速数字隔离器 [High Speed Digital Isolators]
分类和应用: 逻辑集成电路光电二极管
文件页数/大小: 12 页 / 448 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Electrical Specifications  
Test conditions that are not specified can be anywhere within the recommended operating range.  
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0V.  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Units Test Conditions  
Quiescent Supply Current 1  
IDD1  
mA  
VIN = 0V  
HCPL-9000/-0900  
HCPL-9030/-0930  
HCPL-9031/-0931  
HCPL-900J/-090J  
HCPL-901J/-091J  
HCPL-902J/-092J  
0.012  
0.012  
2.5  
0.024  
5.0  
0.018  
0.018  
3.0  
0.036  
6.0  
2.5  
3.0  
Quiescent Supply Current 2  
IDD2  
mA  
VIN = 0V  
HCPL-9000/-0900  
HCPL-9030/-0930  
HCPL-9031/-0931  
HCPL-900J/-090J  
HCPL-901J/-091J  
HCPL-902J/-092J  
5.0  
5.0  
2.5  
8.0  
5.0  
6.0  
6.0  
6.0  
3.0  
12.0  
6.0  
9.0  
Logic Input Current  
IIN  
-10  
10  
µA  
V
Logic High Output Voltage  
VOH  
VDD2 0.1  
VDD2  
IOUT= -20 µA, VIN= VIH  
IOUT= -4 mA, VIN= VIH  
IOUT= 20 µA, VIN= VIL  
IOUT= 4 mA, VIN= VIL  
0.8 V  
*
VDD2 0.5  
V
DD2  
Logic Low Output Voltage  
VOL  
0
0.1  
0.8  
V
0.5  
V
Switching Specifications  
Maximum Data Rate  
100  
110  
MBd  
MHz  
ns  
CL = 15 pF  
Clock Frequency  
fmax  
tPHL  
50  
15  
Propagation Delay Time to Logic  
Low Output  
10  
10  
Propagation Delay Time to Logic  
High Output  
tPLH  
15  
3
ns  
Pulse Width  
tPW  
10  
ns  
ns  
Pulse Width Distortion[1]  
|PWD|  
2
|tPHL tPLH  
|
Propagation Delay Skew[2]  
Output Rise Time (10 90%)  
Output Fall Time (10 90%)  
tPSK  
tR  
4
1
1
6
3
3
ns  
ns  
ns  
tF  
Propagation Delay Enable to Output (Single Channel)  
High to High Impedance  
Low to High Impedance  
High Impedance to High  
High Impedance to Low  
tPHZ  
tPLZ  
tPZH  
tPZL  
tCSK  
3
3
3
3
2
5
5
5
5
3
ns  
ns  
ns  
ns  
ns  
Channel-to-Channel Skew  
(Dual and Quad Channels)  
Common Mode Transient Immunity  
(Output Logic High or Logic Low)[3]  
|CMH|  
|CML|  
15  
18  
kV/µs Vcm = 1000V  
Notes:  
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.  
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.  
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode  
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode  
voltage edges.  
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits  
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to  
complete failure.  
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