V
DD1
V
DD2
+15 V
0.1 µF
∆V
OS
– INPUT OFFSET CHANGE – mV
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-40
-20
0
20
40
60
80
100
V
DD1
= 5 V
V
DD2
= 5 V
1
8
0.1 µF
2
HCPL-7820/7825
3
6
7
10 K
+
0.1 µF
10 K
V
OUT
–
AD624CD
GAIN = 100
4
5
0.47
µF
0.47
µF
-15 V
0.1 µF
T
A
– TEMPERATURE – °C
Figure 1. Input Offset Voltage Test Circuit.
Figure 2. Input Offset Change vs.
Temperature.
∆V
OS
– INPUT OFFSET CHANGE – mV
0.5
vs. V
DD1
(V
DD2
= 5 V)
V
O
– OUTPUT VOLTAGE – V
4.0
3.5
NEGATIVE
OUTPUT
POSITIVE
OUTPUT
0.4
0.3
vs. V
DD2
(V
DD1
= 5 V)
T
A
= 25°C
3.0
2.5
2.0
1.5
1.0
-0.6
V
DD1
= 5 V
V
DD2
= 5 V
T
A
= 25°C
0.2
0.1
0
-0.1
-0.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
-0.4
-0.2
0
0.2
0.4
0.6
V
DD
– SUPPLY VOLTAGE – V
V
IN
– INPUT VOLTAGE – V
Figure 3. Input Offset Change vs. V
DD1
and V
DD2
.
Figure 4. Output Voltages vs. Input
Voltage.
V
DD1
V
DD2
+15 V
0.1 µF
+15 V
0.1 µF
1
8
0.1 µF
V
IN
404
2
HCPL-7820/7825
3
6
7
0.1 µF
10 K
+
+
13.2
0.01 µF
10 K
V
OUT
–
AD624CD
GAIN = 4
–
AD624CD
GAIN = 10
4
5
0.47
µF
0.47
µF
-15 V
0.1 µF
0.1 µF
-15 V
10 K
0.47
µF
Figure 5. Gain and Nonlinearity Test Circuit.
1-241
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
