Application Information
0.1 µF. For each capacitor, the
total lead length between both
ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 13
illustrates the recommended
printed circuit board layout for
the HPCL-x710.
connected directly to the inputs
and outputs.
Bypassing and PC Board Layout
The HCPL-x710 optocouplers are
extremely easy to use. No external
interface circuitry is required
because the HCPL-x710 use high-
speed CMOS IC technology
As shown in Figure 12, the only
external components required for
proper operation are two bypass
capacitors. Capacitor values
should be between 0.01 µF and
allowing CMOS logic to be
V
8
7
6
5
V
DD1
1
2
3
4
DD2
C1
C2
V
I
NC
NC
V
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 12. Recommended Printed Circuit Board layout.
V
DD1
V
V
DD2
V
I
C1
C2
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 13. Recommended Printed Circuit Board layout.
Propagation Delay, Pulse-Width
Distortion and Propagation Delay
Skew
tion delay from low to high (tPLH
)
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low. See
Figure 14.
is the amount of time required for
an input signal to propagate to the
output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
Propagation Delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
INPUT
5 V CMOS
V
50%
0 V
I
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
10%
10%
O
V
OL
Figure 14.
9
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