I
F
B
R
M
D.U.T.
V
CC
A
R
L
V
O
+5 V
V
FF
GND
SINGLE CHANNEL OR
COMMON V
CC
DEVICES
V
CM
-
+
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
5V
V
CC
220
Ω
D.U.T.
V
CC
TTL
LOGIC GATE
0.01 µF
GND
EACH CHANNEL
R
L
Logic Family
Device No.
V
CC
R
L
5% Tolerance
LSTTL
54LS14
5V
18 kΩ *
CMOS
CD40106BM
5V
8.2 kΩ
15 V
22 kΩ
*The equivalent output load resistance is affected by the LSTTL input current and is
approximately 8.2 kΩ. This is a worst case design which takes into account 25%
degradation of CTR. See App. Note 1002 to assess actual degradation and lifetime.
Figure 11. Recommended Logic Interface.
V
CC
D.U.T.*
V
CC
(EACH INPUT)
+
V
IN
-
0.1 µF
V
O
GND
NOMINAL CONDITIONS
PER CHANNEL: I
F
= 20 mA
I
O
= 4 mA
I
CC
= 30 µA
NOTE: BASE LEAD NOT CONNECTED.
T
A
= +125 ˚C
(EACH OUTPUT)
V
OC
Figure 12. Operating Circuit for Burn-In and
Steady State Life Tests. All Channels Tested
Simultaneously.
12
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
