5
Switching Specifications
Over recommended temperature (T
A
= -40°C to 85°C), V
CC
= 5 V, I
F
= 7.5 mA unless otherwise specified.
Parameter
Propagation
Delay Time
to High
Output Level
Propagation
Delay Time
to Low
Output Level
Propagation
Delay Skew
Symbol
t
PLH
Device
HCPL- Min. Typ.* Max. Unit
20
48
75
100
t
PHL
25
50
75
100
t
PSK
3.5
24
10
t
fall
10
10
|CM
H
|
M600
M601
10,000
5,000 10,000
V/µs V
CM
= 10 V
V
O(min)
= 2 V
R
L
= 350
Ω
V
CM
= 50 V
I
F
= 0 mA
V
CM
= 1000 V T
A
= 25°C
11
7, 9
40
35
C
L
= 15 pF
9
T
A
= 25°C
R
L
= 350
Ω
ns
Test Conditions
T
A
= 25°C
Fig. Note
6, 7
8
6, 7
8
10,
11
10
6
5
Pulse Width |t
PHL
- t
PLH
|
Distortion
Output Rise
Time
(10%-90%)
Output Fall
Time
(10%-90%)
Common
Mode
Transient
Immunity at
High Output
Level
Common
Mode
Transient
Immunity at
Low Output
Level
t
rise
M611 10,000 15,000
|CM
H
|
M600
M601
10,000
5,000 10,000
M611 10,000 15,000
V
O(max)
= 0.8 V 11
R
L
= 350
Ω
V
CM
= 50 V
I
F
= 7.5 mA
V
CM
= 1000 V T
A
= 25°C
V
CM
= 10 V
8, 9
*All typicals at T
A
= 25°C, V
CC
= 5 V.
Notes:
1. Bypassing of the power supply line is required with a 0.1
µF
ceramic disc capacitor adjacent to each optocoupler. The total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 20 mA.
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
≥
3000 V
RMS
for 1 second
(Leakage detection current limit, I
I-O
≤
5
µA).
5. The t
PLH
propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
6. The t
PHL
propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
7. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., V
OUT
> 2.0 V).
8. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., V
OUT
> 0.8 V).
9. For sinusoidal voltages, (|dV
CM
|/dt)
max
=
πf
CM
V
CM(p-p)
.
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within
the worst case operating condition range.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
