5) Testing
sense connections are provided
to allow the use of remote-
sensing power supplies of
compensation for PCB traces and
cable resistance.
2) Circuit Operation
- Signal Source
The design of the power module
(PAM) provide bias control via
Vcntl to achieve optimal RF
performance and power control.
The control pin is labeled Vcntl.
Please refer to for the block
diagram of this PAM.
The CDMA modulated signal for
the test is generated using an
Agilent ESG-D4000A (or ESG-
D3000A) Digital Signal Generator
with the following settings:
- Device Operation
1) Connect RF Input and Output
for the band under test.
2) Terminate all unused RF
ports into 50 Ohms.
3) Connect Vdd1, Vdd2 and
Vdd3 supplies (including
remote sensing labeled
Vdd1 S, Vdd2 S and Vbias S
on the board). Nominal
voltage is 3.4V.
CDMA Setup : Reverse
Spreading: On
Bits/Symbol: 1
Typical Operation Conditions
(Vdd1=Vdd2=Vbias = 3.4V)
Data: PN15
Modulation: OQPSK
Chip Rate: 1.2288 Mcps
High Crest: On
Filter: Std
Phase Polarity: Invert
Parameter
ACPM-7833
Frequency Range
Output Power
Vcntl
1850 – 1910 MHz
28.5 dBm
2.5 V
4) Connect Vcntl supply and set
reference voltage to the
voltage shown in the data
packet. Note that the Vcntl pin
is on the back side of the
demonstration board. Please
limit Vcntl to not exceed the
corresponding listed “DC
Biasing Condition” in the Data
Packet. Note that increasing
Vcntl over the corresponding
listed “DC Biasing Condition”
can result in power decrease
and current can exceed the
rated limit.
- ACPR Measurement
The ACPR (and channel power) is
measured using an Agilent 4406
VSA with corresponding ACPR
offsets for IS-98c and JSTD-8.
Averaging of 10 is used for ACPR
measurements.
3) Maximum Ratings
Vdd
5.0V
Drain Current
Vcntl
1.5A
3V
RF input
Temperature
10 dBm
-30 to 85°C
- DC Connection
Please Note: Avoid Electrostatic Discharge
on all I/O’s.
A DC connector is provided to
allow ease of connection to the
I/Os. Wires can be soldered to
the connector pins, or the
connector can be removed and
I/Os contacted via clip leads or
direct soldered connections. The
wiring of I/Os are listed in
Figures 20 through 23 and the
Pin configuration table. The Vdd
4) Heat Sinking
The demonstration PC Board
provides an adequate heat sink.
Maximum device dissipation
should be kept below 2.5 Watts.
5) Apply RF input power accord-
ing to the values listed in
“Operation Data” in Data
Packet.
6) Power down in opposite
sequence.
Vbias
Vdd2
Vdd1
Bias Circuit
On Chip
Inter-stage
Match
Passive
Output
Match
Passive
Input
Match
Input
Output
Vcntl
Single control bias setting for low Idq
and 40% PAE at Pout = 28.5 dBm
Figure 24. Power Module Block Diagram.
19
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
