VDD
Aux.
RF
Drain
Output
Aux.2nd
RF
Gate Bias
Input
Aux.
Temp.
Chip ID No.
Gate Bias
Diode Sense
Temp.
VG1
Extra
Diode Sense
(VDD & Aux
Drain Pads)
70
2910
Gate Bias
(RF Output Pad)
690
555
555
770
(± 10)
285
75
220
0
1690
1890
70
2900
(VG2
Pad
(RF Input Pad)
0
)
2090
2290
2490
2980
(± 10)
Notes:
Figure 2.
TC724 Bond Pad Locations
•
•
All dimensions in microns.
RF input and output Pads
Dim.: 75 × 75 µm.
•
•
Polygon Pad Dim.: 95 µm dia.
All other dimensions: ± 5 µm
(unless otherwise noted).
1.5 mil dia. Gold Wire
Bond to ≥15 nF
DC Feedthru
•
Chip thickness: 127 ± 15 µm.
(0160-5052)
≥68 pF Chip Capacitor
≥4nH Inductor
(5086-2116)
1.0 mil Gold Wire Bond
(Length ≥150 mils)
Input & Output Thin Film
Circuit w/≥ pF
Gold Plated Shim
(5021-8739)
Trace Offset
168 µm
DC Blocking Capacitor
( 0160-5674)
(6.6 mils)
2.0 mil
nom. gap
Notes:
V
DD
OUT
•
Part Numbers for recommended Agi-
lent components shown in
parenthesis.
TC724
V
IN
G1
Trace Offset
168 µm
•
Total offset between RF input and RF
output pad is 335 µm (13.2 mils).
(6.6 mils)
2.0 mil
nom. gap
Bonding Island
(3980-0442)
0.7 mil dia. Gold Bond Wire
(Length NOT important)
1.5 mil dia Gold Wire
Bond to ≥15 nF DC Feedthru
(0160-5052)
Figure 3.
TC724 Assembly Diagram
(For 2.0–26.5 GHz Operation)
4
TC724/rev.3.3
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
