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T9000 参数 Datasheet PDF下载

T9000图片预览
型号: T9000
PDF下载: 下载PDF文件 查看货源
内容描述: ISDN网络终端节点( NTN )设备 [ISDN Network Termination Node (NTN) Device]
分类和应用: 综合业务数字网
文件页数/大小: 126 页 / 1581 K
品牌: AGERE [ AGERE SYSTEMS ]
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T9000  
Preliminary Data Sheet  
November 2000  
ISDN Network Termination Node (NTN) Device  
Table of Contents (continued)  
Page Figures  
Tables  
Page  
Table 117. Absolute Maximum Ratings ..................110  
Table 118. ESD Threshold Voltage ........................110  
Table 119. Recommended Operating Conditions .110  
Table 120. Power Consumption ............................111  
Table 121. S/T-Interface Receiver Common-Mode  
Rejection...............................................................111  
Table 123. Digital dc Characteristics (Over  
Operating Ranges)................................................112  
Table 123. Fundamental Mode Crystal  
Characteristics ......................................................113  
Table 124. Internal PLL Characteristics ..................113  
Table 126. MTC (Master Timing Clock)  
Figure 1. NTN Block Diagram..................................... 6  
Figure 2. T9000 Pinout............................................... 7  
Figure 3. NTN Data Memory Address Space ........... 18  
Figure 4. External Program Memory Read Cycle..... 27  
Figure 5. External Data Memory Read Cycle ........... 27  
Figure 6. External Data Memory Write Cycle ........... 28  
Figure 7. Downstream EOC Analysis (AUTOEOC = 1)  
and Upstream EOC Processing............................. 31  
Figure 8. 2B+D Data Flow Block Diagram................ 32  
Figure 9. HDLC Transmitter FIFO ............................ 53  
Figure 10. HDLC Receiver Status Word................... 54  
Figure 11. HDLC Receiver FIFO Snapshot  
Requirements and Characteristics (LT Mode) ......113  
Table 126. Register Set Summary Global  
Sequence............................................................... 55  
Figure 12. DLCI Extension and Function of  
Registers .............................................................118  
Table 127. Register Set Summary DFAC  
SAPI0M-TEI0M Bits............................................... 57  
Figure 13. GCI+ Interface, TDM Mode Timing,  
Registers .............................................................118  
Table 128. Register Set Summary U-Interface  
Control Registers ..................................................118  
Table 129. Register Set Summary EOC  
Double Clock Mode: GCCF[CKMODE] = 0,  
GCCF[GMODE(1:0)] = 1x...................................... 71  
Figure 14. GCI+ Interface, TDM Mode Timing,  
Single Clock Mode: GCCF[CKMODE] = 1,  
Control Registers ................................................119  
Table 130. Register Set Summary S-Interface  
Registers ..............................................................119  
Table 131. Register Set Summary Multiframe  
Registers .............................................................119  
Table 132. Register Set Summary U-Interface  
Interrupt Registers ..............................................119  
Table 133. Register Set Summary S-Interface  
Interrupt Registers ...............................................120  
Table 134. Register Set Summary HDLC  
Registers ..............................................................121  
Table 135. Register Set Summary GCI+  
Registers ..............................................................123  
Table 136. Register Set Summary GPIO  
Registers ..............................................................124  
Table 137. Register Set Summary PWM  
Registers ..............................................................125  
Table 138. Register Set Summary dc/dc  
GCCF[GMODE(1)] = 1........................................... 72  
Figure 15. NTN/T8503 Glueless TDM  
Interconnection ...................................................... 72  
Figure 16. GCI-NT Frame Structure ......................... 74  
Figure 17. GCI-NT Timing Diagram.......................... 74  
Figure 18. GCI-TE Mode Frame Structure ............... 76  
Figure 19. GCI Loopback Logic................................ 78  
Figure 20. GPIO Pin Capabilities Summary ............. 86  
Figure 21. Pulse-Width Modulated Output Signal .... 93  
Figure 22. PWMCNTRL Architecture ....................... 95  
Figure 23. Widths of PWM Pulses Generated with  
a 2.5%—97.5% Modulation Width ......................... 99  
Figure 24. (A) CMV When CME Is a Periodic  
Pulse and (B) CMV When CMV Is Static ............. 105  
Figure 25. Location of the Loopback  
Configurations...................................................... 109  
Figure 26. NT1 Application..................................... 114  
Figure 27. NT1+ Application................................... 114  
Figure 28. Pair Gain Application............................. 115  
Register ................................................................125  
Table 139. Register Set Summary Comparator  
Registers ..............................................................126  
Lucent Technologies Inc.  
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