Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Pin Information
(continued)
Table 2. Pin Descriptions
(continued)
Pin
21
Symbol
CLKR/DRB
Type
I
Name/Function
Receive Clock or Receive Data B.
The functionality of this pin is controlled by
programming the P21CTL bit in the receiver control register (R5—B6). When
P21CTL is cleared to 0 (default), this pin is the receive data clock (CLKR).
Receive clock frequency must be less than the chip master clock frequency
divided by 2 (fCLKR < fCLK/2). Upon reset, data is received (latched) on the ris-
ing edge of CLKR. Data can be received on the falling edge of the receive clock
by clearing the CLKRI bit in register 9 (R9—B0) to 0. Receive clock rate can be
independent of transmit clock rate.
When P21CTL (R5—B6) is set to 1, this pin is configured as Receive Data B
(DRB). Clocking for receive data is obtained from CLKX, while CLKRI (R9—B0)
controls the edge of CLKX used to latch received data. In this mode, data can
be received on DRA or on DRB. DRB is selected by setting the DRA/B bit in reg-
ister 8 (R8—B7) to 1. Data can be optionally inverted (DRI, R11—B7) and
received during a user-selected time slot (registers 8, 9, 11) with bit 0 or bit 7
first (RLBIT R11—B6).
Clock.
This clock controls internal chip operation. It can be from 0 MHz to
12 MHz. Typically it is 6.144 MHz (i.e., SYSCKO from the Lucent T7250C).
Clock frequency must be greater than two times the fastest data clock fre-
quency.
Address Bus.
These four address leads allow the chip to be accessed by a
microprocessor employing separate address and data leads. They are used to
select the internal registers. The ALE pin should be tied high in this mode of
operation.
These pins can be left unconnected when in the multiplexed address/data mode
(internal pull-up resistors are provided).
+5 V Supply.
23
CLK
I
24, 25, 26,
27
A3—A0
I
28
V
DD
—
Lucent Technologies Inc.
7
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