T7121 HDLC Interface for ISDN (HIFI-64)
Data Sheet
April 1997
Pin Information
ALE
AD0
AD1
AD2
AD3
V
SS
AD4
AD5
AD6
AD7
WR
RD
CS
INT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LUCENT
T7121
HIFI-64
V
DD
A0
A1
A2
A3
CLK
V
SS
CLKR/DRB
DRA
DXA
CLKX
DXB/TSCA
FS
RESET
5-5028
Figure 2. Pin Diagram
Table 1. Pin Assignments
Group
Chip Clock
Power & Ground
Microprocessor Bus Interface
Symbol
CLK
V
DD
V
SS
RD
WR
CS
Function
0 MHz—12 MHz
5 V Power
Ground
Read
Write
Chip Select
Interrupt
Reset
Address/Data Bus
Address Latch Enable
Address Bus (non-ALE addressing mode)
Transmit Data A
Transmit Data B
Time-slot Control DXA
Transmit Clock
Frame Synchronization
Receive Clock
Receive Data A
Receive Data B
INT
RESET
AD7—AD0
ALE
A3—A0
Serial Link Interface
DXA
DXB
TSCA
CLKX
FS
CLKR
DRA
DRB
4
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
