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T7121 参数 Datasheet PDF下载

T7121图片预览
型号: T7121
PDF下载: 下载PDF文件 查看货源
内容描述: T7121 HDLC接口ISDN [T7121 HDLC Interface for ISDN]
分类和应用: 综合业务数字网
文件页数/大小: 68 页 / 652 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
April 1997  
T7121 HDLC Interface for ISDN (HIFI-64)  
Functional Description (continued)  
Bit Masking  
When in the TDM highway mode (HWYEN, R0—B7 = 1), the HIFI-64 can be programmed to mask any combina-  
tion of bits in a byte. As an example, this feature is used to process 16 kbits/s D-channel data where only 2 bits in  
each byte are looked at when receiving, and where only 2 bits are transmitted during an 8-bit time slot. Using this  
option, the HIFI-64 is able to support effective intermediate data rates of 8, 16, 24, 32, 40, 48, and 56 kbits/s.  
The receiver ignores bit positions that are masked (cleared to 0) in the receiver bit mask register (R12). The trans-  
mitter outputs high impedance (3-state) during the bit times specified (cleared to 0) in the transmitter bit mask reg-  
ister (R13). The user can program any combination of bits to be masked in the receiver and transmitter  
independently.  
Upon chip reset, the default is as follows:  
1. The receiver defaults to recognize all incoming data as valid (i.e., no masking).  
2. The transmitter defaults to a state where all bits are masked.  
The user must unmask the bits to be transmitted.This eliminates the problem of the HIFI-64 transmitting before the  
time slot has been programmed in registers 7, 9, and 10.  
Figures 8 and 9 show how 16 kbits/s operation is achieved by using the bit-masking option.  
16  
Lucent Technologies Inc.