Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
432-Pin EBGA Pinout, 177
600-Pin EBGA Pinout, 184
Package Compatibility, 152
Pin Descriptions 147, 151
Power Dissipation, 144
5 V Tolerant I/O, 143
OR3Cxx, 144
OR3Txxx, 145
PowerPC (see Microprocessor Interface)
Programmable Clock Manager (PCM), 6, 81
Clock Delay, 74
Index (continued)
L
Look-Up Table (LUT) Operating Modes, 11—18
Adder-Subtractor Submode, 15
Counter Submode, 15
Equality Comparators, 16
Half-Logic Mode, 14
Logic Mode, 12
Memory Mode, 17
Multiplier Submode, 16
Ripple Mode, 14
Clock Multiplication, 75
DLL Mode, 73
PCM Cautions, 81
LSR, 11, 17, 23—24, 31, 48
PCM Detailed Programming, 77
PCM Operation, 76
PCM/FPGA Internal Interface, 76
PLL Mode, 74
M
Maximum Ratings (see Absolute Maximum Ratings)
Microprocessor Interface (MPI), 62—69
i960 System, 64
Registers, 71
Programmable Function Unit (PFU), 9
Cintrol Inputs, 11
Interface to FPGA, 65
PowerPC System, 63
Operating Modes, 11
Softwired LUTs (SWL), 12
Twin-quad Architecture, 1, 8, 14, 19
Programmable Input/Output Cells (PICs), 34—44
5 V Tolerant I/O, 35
Architecture, 43
Setup and Control Registers, 66
Multiplexing (see Output Multiplexing)
Multiplier (see LUT Operating Modes)
O
ORCA Foundry Development System, 25
Overview, 7
Ordering Information
Control Inputs, 11, 23
ASWE, 11
CE, 11
CLK, 11
Package Matrix, 207
Package Options, 207
Temperature Options, 207
Voltage Options, 207
Output (see PICs)
GSRN, 11, 24
LSR, 11
SEL, 11
Input Demultiplexing, 38
Inputs, 36
Output Multiplexing, 39
Output Multiplexing, 39
Outputs, 39
P
Open-Drain Output Option, 39
Propagation Delays, 39
Overview, 32
PIO, 34
PIO Logic, 41
Package Information, 200—206
Package Matrix, 204
Package Outline Diagrams, 200
208-Pin SQFP2, 199
240-Pin SQFP2, 202
256-Pin PBGA, 203
PIO Options, 35
PIO Register Control Signals, 41
Zero-Hold Input, 37
Programmable Logic Cells (PLCs), 9—33
Architecture, 32
352-Pin PBGA, 204
432-Pin EBGA, 205
600-Pin EBGA, 206
Terms and Definitions, 200
PAL, 1 (see also Supplemental Logic and
Interconnect Cell (SLIC)) 1
PIC Routing (see Routing)
Pin Information
208-Pin SQFP2 Pinout, 151
240-Pin SQFP2 Pinout, 156
256-Pin PBGA Pinout, 162
352-Pin PBGA Pinout, 165
208
Latches/Flip-Flops, 23, 24
PFU, 9
Propagation Delays (see PICs, Outputs)
Routing, 25
SLIC, 19—22
Lucent Technologies Inc.
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