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OR3T55-6BA256 参数 Datasheet PDF下载

OR3T55-6BA256图片预览
型号: OR3T55-6BA256
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
Special Function Blocks (continued)  
Boundary-Scan Timing  
To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on  
the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST  
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-  
quency allowed for TCK is 10 MHz.  
Figure 41 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to  
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is  
clocked into the DUT on the rising edge.  
TCK  
TMS  
TDI  
5-5971(F)  
Figure 41. Instruction Register Scan Timing Diagram  
Lucent Technologies Inc.  
63