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OR3T55-6BA256 参数 Datasheet PDF下载

OR3T55-6BA256图片预览
型号: OR3T55-6BA256
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
Clocks in the PICs  
Clock Distribution Network (continued)  
Because the Series 3 FPGAs have latches and FFs in  
the I/Os, it is necessary to have clock signal distribution  
to the PIOs as well as in the PLC array. The system  
clock, the fast clock, and the ExpressCLK are available  
for PIO clocking.  
Clock Sources to the PLC Array  
The source of a clock that is globally available to the  
PLC array can be from any user I/O pad, any of the  
ExpressCLK pads, or an internally generated source.  
System Clock  
PIC System Clock  
As described in the Programmable Input/Output Cells  
section, PICs are grouped in adjacent pairs. Any one of  
the eight pads in a PIC pair can drive a clock spine in a  
row or column. For PIC pairs on the top of the chip, the  
column associated with the left PIC has the clock  
spine, for pairs on the bottom, the right PIC column has  
the spine. The top PIC of the pair sources the spine  
from the left side of the array, and the bottom PIC of the  
pair sources the spine from the right side of the array.  
Clock delay and skew are minimized by having a single  
clock buffer per pair of PICs. The clock spine for each  
pair can also be driven by one of the four PIC switching  
segments (pSW) in each PIC of the pair. This allows a  
signal generated in the PLC array to be routed onto the  
global clock spine network. The system clock output of  
the programmable clock manager (PCM) may also be  
routed to the global system clock spines via the pSW  
segments. Figure 33 shows the clock spine multiplex-  
ing structure for a pair of PICs on the top of the array.  
There are five local system clock lines in each PIC.  
Much like the sources for a clock in the PFU, two of the  
local PIC clocks are generated within the PIC from long  
lines. One is generated from the set of ten PIC long  
lines (pxL) that runs parallel to the PICs on a side, and  
the other is generated from the set of ten long lines (xL)  
from the PLC array that terminate in the PIC. Another  
local PIC system clock route comes from the set of ten  
xL lines in the adjacent PLC that is parallel to the side  
of the array on which the PIC resides. The fourth local  
PIC system clock route comes from the set of ten long  
lines (xL) from the PLC array that terminate in the adja-  
cent PIC that is not part of the same PIC pair. Much like  
the E1 signals in the PLCs that are used to distribute a  
local clock to the PFU source, the fifth local clock line in  
each PIC comes from local pSW signals. This clock  
signal for each PIC is shown in Figure 33. One of these  
five local PIC system clocks is selected for the system  
clock signal in the PIO. It is used as the PIO system  
clock for both input and output clocking as selected  
within the PIO. All PIOs in a PIC share the same sys-  
tem clock.  
Fast Clock  
The fast clock spines are sourced to the PLC array  
from each side of the device by the ExpressCLK pads  
via the CLKCNTRL function block (described in the  
Special Function Blocks section). The ExpressCLK and  
fast clock source from the pads is shown in Figure 34  
and will be described further in the ExpressCLK Inputs  
subsection.  
PIC ExpressCLK  
The ExpressCLK signal used at the PIC latches/FFs  
comes from the CLKCNTRL function block that resides  
in the middle of the side on which the PIC resides. A  
single signal comes from the CLKCNTRL and is driven  
by separate buffers onto two ExpressCLK long wires.  
One of these ExpressCLK signals goes to the PICs on  
the right of (above) the CLKCNTRL block, and the  
other ExpressCLK signal goes to the PICs on the left of  
(below) the CLKCNTRL block on that side.  
PAD A  
PAD B  
PAD C  
PAD D  
pSW[4]  
pSW[5]  
pSW[6]  
pSW[7]  
TO LOCAL CLOCKS  
TO LOCAL CLOCKS  
TPICR  
SPINE  
TPICL  
5-5800(F)  
Figure 33. PIC System Clock Spine Generation  
52  
Lucent Technologies Inc.