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OR3T55-6BA256 参数 Datasheet PDF下载

OR3T55-6BA256图片预览
型号: OR3T55-6BA256
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
Clock Distribution Network  
is generated from the PLC to the left or right of the cur-  
rent PLC, and one is generated from the PLC above or  
below the current PLC. The selection decision as to  
where these signals come from, above/below and left/  
right, is based on the position of the PLC in the array  
and has to do with the alternating nature of the source  
of the system clock spines (discussed later). The last of  
the five clock sources is also generated within the PLC.  
The E1 control signal, described in the PLC Routing  
Resources section, can drive the PFU clock. The E1  
signal can come from any xBID routing resource in the  
PLC. The selection and switching of clock signals in a  
PLC is performed in the FINS. Figure 31 shows the  
PFU clock sources for a set of four adjacent PLCs.  
The Series 3 FPGAs provide three types of high-  
speed, low-skew clock distributions: system clock, fast  
middle clock (fast clock), and ExpressCLK. Because of  
the great variety of sources and distribution for clock  
signals in the ORCA Series 3, the clock mechanisms  
will be described here from the inside out. The clock  
connections to the PFU will be described, followed by  
clock distribution to the PLC array, clock sources to the  
PLC array, and finally ending with clock sources and  
distribution in the PICs. The ExpressCLK inputs are  
new, dedicated clock inputs in Series 3 FPGAs. They  
are mentioned in several of the clock network descrip-  
tions and are described fully later in this section.  
Global Control Signals  
The four clock signals in each PLC that are generated  
from the long lines (xL) in the current PLC or an adja-  
cent PLC can also be used to drive the PFU clock  
enable (CE), local set/reset (LSR) and add/subtract/  
write enable (ASWE) signals. The clock signals gener-  
ated from vertical long lines can drive CE and ASWE,  
and the clocks generated from horizontal long lines can  
drive LSR. This allows for low-skew global distribution  
of two of these three control signals with the clock rout-  
ing while still allowing a global clock route to occur.  
PFU Clock Sources  
Within a PLC there are five sources for the clock signal  
of the latches/FFs in the PFU. Two of the signals are  
generated off of the long lines (xL) within the PLC: one  
from the set of vertical long lines and one from the set  
of horizontal long lines. For each of these signals, any  
one of the ten long lines of each set, vertical or horizon-  
tal, can generate the clock signal. Two of the five PFU  
clock sources come from neighboring PLCs. One clock  
vxL[9:0]  
vxL[9:0]  
PLC  
PLC  
PFU  
PFU  
E1  
E1  
hxL[9:0]  
PLC  
PLC  
PFU  
PFU  
E1  
E1  
hxL[9:0]  
5-6054(F)  
Figure 31. PFU Clock Sources  
50  
Lucent Technologies Inc.