Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells (continued)
Zero-Hold Input
There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from
the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system
clock.
To guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. The
fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sources the input FF data
from a dedicated latch that is clocked by the ExpressCLK from the PIC. The ExpressCLK is a clock from a dedi-
cated input pin designed for fast, low-skew operation at the I/Os and is described more fully in the Clock Distribu-
tion Network and PIC Interquad (MID) Routing sections that follow. The combination of ExpressCLK latch and
system clock FF guarantees a zero-hold capture of input data in the PIO FF, while at the same time reducing input
setup time. Figure 23 shows a schematic of the fast-capture latch/FF and a sample timing diagram.
FF
LATCH
D Q
DATA OUT
TO PIC ROUTING
INPUT DATA
D
Q
O
I
EXPRESSCLK
CLK
CE
S/R
CD = 1
O
I
SYSTEM CLK
CLOCK ENABLE
LOCAL SET/RESET
EXPRESSCLK
SYSTEM CLK
INPUT DATA
A
B
C
D
E
E
D
A
B
C
D
QLATCH
QFF
A
B
C
5-5974(F)
Note: CE and LSR signals not shown.
Figure 23. Fast-Capture Latch and Timing
Lucent Technologies Inc.
39
AGERE [ AGERE SYSTEMS ]
