Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
The latches/FFs can be configured in three basic
modes:
Programmable Logic Cells (continued)
The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF. A new option is available to disable the
GSRN function per PFU after initial device configura-
tion.
1. Local synchronous set/reset: the input into the
PFU’s LSR port is used to synchronously set or
reset each latch/FF.
2. Local asynchronous set/reset: the input into LSR
asynchronously sets or resets each latch/FF.
3. Latch/FF with front-end select, LSR either synchro-
nous or asynchronous: the data select signal
selects the input into the latches/FFs between the
LUT output and direct data in.
The latch/FF can be configured to have a data front-
end select. Two data inputs are possible in the front-
end select mode, with the SEL signal used to select
which data input is used. The data input into each
latch/FF is from the output of its associated LUT, F[7:0],
or direct from DIN[7:0], bypassing the LUT. In the front-
end data select mode, both signals are available to the
latches/FFs.
For all three modes, each latch/FF can be indepen-
dently programmed as either set or reset. Figure 17
provides the logic functionality of the front-end select,
global set/reset, and local set/reset operations.
The ninth PFU FF, which is generally associated with
registering the carry-out signal in ripple mode func-
tions, can be used as a general-purpose FF. It is only
an FF and is not capable of being configured as a latch.
Because the ninth FF is not associated with an LUT,
there is no front-end data select. The data input to the
ninth FF is limited to the CIN input, logic 1, logic 0, or
the carry-out in ripple and half-logic modes.
If either or both of these inputs is unused or is unavail-
able, the latch/FF data input can be tied to a logic 0 or
logic 1 instead (the default is logic 0).
CE/ASWE
CE
SEL
CE/ASWE
CE/ASWE
F
DIN
LOGIC 1
LOGIC 0
F
DIN
LOGIC 1
CE
F
DIN
LOGIC 1
CE
D
Q
D
Q
Q
D
DIN
LOGIC 0
LOGIC 0
s_set
LSR
s_reset
CLK
GSRN
LSR
GSRN
LSR
CLK
SET RESET
CLK
SET RESET
SET RESET
GSRN
CD
CD
CD
Key: C = configuration data.
Figure 17. Latch/FF Set/Reset Configurations
26
Lucent Technologies Inc.
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