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OR3T55-6BA256 参数 Datasheet PDF下载

OR3T55-6BA256图片预览
型号: OR3T55-6BA256
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
Pin Information  
Pin Descriptions  
This section describes the pins found on the Series 3 FPGAs. Any pin not described in this table is a user-program-  
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.  
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled  
after configuration.  
Table 67. Pin Descriptions  
Symbol  
I/O  
Description  
Dedicated Pins  
DD  
V
Positive power supply.  
Ground supply.  
GND  
DD  
DD  
V
5
5 V tolerant select. V 5 pin locations are shown for package compatibility with  
OR2TxxA devices. Connections to 5 V power sources are not used for 5 V tolerant  
I/Os in the OR3Txxx devices.  
RESET  
CCLK  
I
I
During configuration, RESET forces the restart of configuration and a pull-up is  
enabled. After configuration, RESET can be used as a general FPGA input or as a  
direct input, which causes all PLC latches/FFs to be asynchronously set/reset.  
In the master and asynchronous peripheral modes, CCLK is an output which  
strobes configuration data in. In the slave or synchronous peripheral mode, CCLK  
is input synchronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK  
is used internally and output for daisy-chain operation.  
DONE  
I
As an input, a low level on DONE delays FPGA start-up after configuration (see  
Note).  
O
I
As an active-high, open-drain output, a high level on this signal indicates that config-  
uration is complete. DONE has an optional pull-up resistor.  
PRGM  
PRGM is an active-low input that forces the restart of configuration and resets the  
boundary-scan circuitry. This pin always has an active pull-up.  
RD_CFG  
I
This pin must be held high during device initialization until the INIT pin goes high.  
This pin always has an active pull-up.  
During configuration, RD_CFG is an active-low input that activates the TS_ALL func-  
tion and 3-states all of the I/O.  
After configuration, RD_CFG can be selected (via a bit stream option) to activate the  
TS_ALL function as described above, or, if readback is enabled via a bit stream  
option, a high-to-low transition on RD_CFG will initiate readback of the configuration  
data, including PFU output states, starting with frame address 0.  
RD_DATA/TDO  
O
I
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con-  
figuration data out. If used in boundary scan, TDO is test data out.  
Special-Purpose Pins  
M0, M1, M2  
During powerup and initialization, M0—M2 are used to select the configuration  
mode with their values latched on the rising edge of INIT; see Table 34 for the config-  
uration modes. During configuration, a pull-up is enabled.  
I/O After configuration, these pins are user-programmable I/O (see Note).  
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE  
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the  
activation of all user I/Os) is controlled by a second set of options.  
Lucent Technologies Inc.  
149