Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
set up at the FPGA pins by the i960 at the next rising
edge of the clock. At this same rising clock edge, the
i960 asserts its address/data strobe (ADS) low. Data is
available to the MPI during a write at the rising clock
edge of the following clock cycle. The transfer is
acknowledged to the i960 by the low assertion of the
ready/recover (RDYRCV) signal. The same process
applies to a read from the MPI except that the read
data is expected at the FPGA data pins by the i960 at
the rising edge of the clock when RDYRCV is low. The
MPI only drives RDYRCV low for one clock cycle.
Microprocessor Interface (MPI) (continued)
i960 System
Figure 44 shows a schematic for connecting the ORCA
MPI to supported i960 processors. In the figure, the
FPGA is shown as the only peripheral, with the FPGA
chip select lines, CS0 and CS1, tied low and high,
respectively. The i960 address and data are multi-
plexed onto the same bus. This precludes memory
mapping of the FPGA in the i960 memory space of a
multiperipheral system without some form of address
latching to capture and hold the address signals to
drive the CS0 and/or CS1 signals. Multiple address sig-
nals could also be decoded and latched to drive the
CS0 and/or CS1 signals. If the MPI is not used for
FPGA configuration, decoding/latching logic can be
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be
routed out an output pin and then connected externally
to CS0 and/or CS1. If the MPI is to be used for configu-
ration, any decode/latch logic used must be imple-
mented external to the FPGA since the FPGA logic has
not been configured yet.
Interrupts can be sent to the i960 asynchronously to
the read/write process. Interrupt requests are sourced
by the user-logic in the FPGA. The MPI will assert the
request to the i960 as a direct interrupt signal and/or a
pollable bit in the MPI status register (discussed in the
MPI Setup and Control section). The MPI will continue
to assert the interrupt request until the user-logic deas-
serts its interrupt request signal.
Table 17.
i960/MPI Configuration
ORCA Pin MPI
i960
Function
Signal
Name
I/O
AD[7:0]
D[7:0]
I/O Multiplexed 5-bit address/
8-bit data bus. The
i960 SYSTEM CLOCK
address appears on D[4:0].
8
ALE
RDY/RCLK/
MPI_ALE
I
Address latch enable used
to capture address from
AD[4:0] on falling edge of
clock.
TO DAISY-
CHAINED
DEVICES
DOUT
CCLK
AD[7:0]
D[7:0]
CLKIN
W/R
RDYRCV
XINTx
ALE
MPI_CLK
MPI_RW
MPI_ACK
MPI_IRQ
ADS
RD
/
MPI_STRB
I
Address/data strobe to
indicate start of transac-
tion.
ORCA
SERIES 3
FPGA
MPI_ALE
MPI_STRB
MPI_BE0
MPI_BE1
i960
ADS
BE0
BE1
CS0
CS1
—
—
I
I
I
Active-low MPI select.
Active-high MPI select.
VDD
DONE
INIT
HDC
LDC
CS1
CS0
System
Clock
A7/
MPI_CLK
i960 system clock. This
clock is sourced by the
system and not the i960.
5-5762(F)
W/
R
A8/MPI_RW
I
Write (high)/read (low)
signal.
Note: FPGA shown as only system peripheral with fixed-chip select
signals. For multiperipheral systems, address decoding and/
or latching can be used to implement chip selects.
RDYRCV
A9/
MPI_ACK
O
Active-low ready/recover
signal indicating acknowl-
edgment of the transac-
tion.
Figure 44. i960/MPI
Any of
XINT[7:0]
A11/
MPI_IRQ
O
I
Active-low interrupt
request signal.
The basic flow of a transaction on the i960/MPI inter-
face is given below. Pin descriptions are shown in
Table 17, and timing is shown in the ORCA Timing
Characteristics section of this data sheet. For both read
and write transactions, the address latch enable (ALE)
is set up by the i960 at the FPGA to the falling edge of
the clock. The address, byte enables, chip selects, and
read/write (read low, write high) signals are normally
BE0
A0/
MPI_BE0
Byte-enable 0 used as
address bit 0 in i960 8-bit
mode.
BE1
A1/
MPI_BE1
I
Byte-enable 1 used as
address bit 1 in i960 8-bit
mode.
66
Lucent Technologies Inc.
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