Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
interrupt the host processor either by a hard interrupt or
by having the host processor poll the microprocessor
interface.
The Series 3 FPGAs have a dedicated synchronous
microprocessor interface function block (see
The control portion of the microprocessor interface is
available following powerup of the FPGA if the mode
pins specify MPI mode, even if the FPGA is not yet con-
figured. The mode pin (M[2:0]) settings can be found in
the FPGA Configuration Modes section of this data
sheet, and the setup and use of the MPI for configura-
tion is discussed in the MPI Setup and Control subsec-
tion. For postconfiguration use, the MPI must be
included in the configuration bit stream by using an MPI
library element in your design from the ORCA macro
library, or by setting the MP_USER bit of the MPI con-
figuration control register prior to the start of configura-
tion (MPI registers are discussed later).
Figure 42). The MPI is programmable to operate with
PowerPC MPC800 series microprocessors and Intel*
i960* J core processors; see Table 16 and Table 17,
respectively, for compatible processors. The MPI imple-
ments an 8-bit interface to the host processor (Pow-
erPC or i960) that can be used for configuration and
readback of the FPGA as well as for user-defined data
processing and general monitoring of FPGA function.
In addition to dedicated-function registers, the micro-
processor interface allows for the control of up to 16
user registers (RAM or flip-flops) in the FPGA logic. A
synchronous/asynchronous handshake procedure is
used to control transactions with user logic in the FPGA
array. There is also capability for the FPGA logic to
* Intel and i960 are registered trademarks of Intel Corporation.
D[7:0]IN
TO FPGA
ROUTING
D[7:0]OUT
ORCA 3C/Txxx MPI
DONE
RD_DATA
INIT
D7IN
D7
D7OUT
D6IN
D6
D5
D4
D3
D2
D1
D0
STATUS
D6OUT
D5IN
REGISTER
D5OUT
D4IN
D4OUT
D3IN
D3OUT
D2IN
D2OUT
D1IN
SCRATCHPAD
REGISTER
D1OUT
D0IN
READBACK
DATA REGISTER
D0OUT
A4
READBACK
ADDR REGISTER
A3
A2
RESET
RD_CFG
PRGM
GSR
C
P
R
E
A1
W
A0
CONTROL
REGISTERS
OP
RD
CS0
CS1
TO GSR BLOCK
IRQ
PART ID
REGISTERS
CCLK
M3
USER_START
USER_END
WR_CTRL
A[3:0]
TO FPGA
ROUTING
M2
M1
M0
MPI_IRQ
RDYRCV
CLK
MPI_ACK
MPI_CLK
MPI_STRB
MPI_ALE
MPI_RW
MPI_B1
i960 LOGIC
ADS
ALE
W/R
RD/WR
BT
POWERPC LOGIC
TS
CLKOUT
TA
DEVICE PAD
I/O BUFFER
5-5806(F)
Figure 42. MPI Block Diagram
64
Lucent Technologies Inc.
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