Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells (continued)
Input Demultiplexing
The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing
provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration
and general timing for demultiplexing a multiplexed address and data signal. The PIO input signal is sent to both
the input latch and directly to IN2. The signal is latched on the falling edge of the clock and output to routing at IN1.
The address and data are then both available at the rising edge of the system clock. These signals may be regis-
tered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the possible use of the SLIC
decoder to perform an address decode to enable which registers are to receive the input data. Although the timing
shown is for using the input register as a latch, it may also be used in the same way as an FF. Also note that the sig-
nals found in PIO inputs IN1 and IN2 can be interchanged.
OTHER ADDRESS
LINES
PIO
PLC
DEC
IN1
IN2
D
Q
PAD
SLIC
SCLK
D
Q
CE
SCLK
PIO INPUT
DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4 DATA4 ADDR5
PIO LATCH
OUTPUT
ADDR1
DATA0
ADDR2
DATA1
ADDR3
DATA2
ADDR4
DATA3
ADDR5
DATA4
PLC FF
OUTPUT
5-5798(F)
Figure 24. PIO Input Demultiplexing
40
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
