Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Table 67. Pin Descriptions
(continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
CS0, CS1
I
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor
configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During config-
uration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O pins (see Note).
RD/
MPI_STRB
I
RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into
a status output. As a status indication, a high indicates ready, and a low indicates busy. WR
and RD should not be used simultaneously. If they are, the write strobe overrides.
I
This pin is also used as the microprocessor interface (MPI) data transfer strobe. For
PowerPC
, it is the transfer start (TS). For
i960
, it is the address/data strobe (ADS).
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
WR
I
WR is used in the asynchronous peripheral configuration mode. When the FPGA is selected,
a low on the write strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR
and RD should not be used simultaneously. If they are, the write strobe overrides.
I/O After configuration, this pin is a user-programmable I/O pin (see Note).
A[17:0]
O
During master parallel configuration mode, A[17:0] address the configuration EPROM. In
microprocessor interface (MPI) mode, many of the A[n] pins have alternate uses as described
below. See the Special Function Blocks section for more MPI information. During configura-
tion, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull-
up enabled.
I/O After configuration, the pins are user-programmable I/O pins (see Note).
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
Lucent Technologies Inc.
151
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