Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Estimating Power Dissipation (continued)
As an example of estimating power dissipation, suppose that a fully utilized OR3T80 has an average of
six outputs for each of the 484 PFUs, that 12 clock branches are used so that the clock is driven to the entire PLC
array, that 250 of the 484 PFUs have FFs clocked at 40 MHz, and that the PFU outputs have an average activity
factor of 20%.
Eighty inputs, 40 of them used as 5 V tolerant inputs, 50 outputs driving 30 pF loads, and 30 bidirectional
I/Os driving 50 pF loads are also generated from the
40 MHz clock with an average activity factor of 20%. All of the output PIOs are registered, and 30 of the input PIOs
are registered.
The worst-case (VDD = 3.6 V) power dissipation is estimated as follows:
PFU
P
= 484 x 6 (0.068 mW/MHz x 20 MHz x 20%)
= 789.9 mW
CLK
P
= [0.107 mW/MHz + (0.09 mW/MHz – Branch)
(12 Branches)
+ (0.015 mW/MHz – PFU) (250 PFUs)
+ (0.004 mW/MHz/PIO) (110 PIOs)]
= 230.43 mW
IN
P
P
P
= 80 x [0.09 mW/MHz x 20 MHz x 20%]
= 28.8 mW
= 50 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%]
= 100.57 mW
= 30 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%]
= 91.45 mW
OUT
BID
TOTAL
= 1.241 W
148
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
