Data Sheet
January 2000
NetLight
1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Transceiver Optical and Electrical Characteristics
(continued)
Table 3. Receiver Optical and Electrical Characteristics
(T
C
= –40
°C
to +85
°C;
V
CC
= 3.135 V to 3.465 V)
Parameter
Average Sensitivity (STM-1/STM-4)*
Maximum Input Power*
Link Status Switching Threshold:
Decreasing Light (STM-1/STM-4)
Increasing Light (STM-1/STM-4)
Link Status Hysteresis
Power Supply Current
Output Data Voltage/Clock Voltage:
Low
High
Output Data/Clock Rise and Fall Times
†
Signal Detect Output Voltage:
Low
High
Clock Duty Cycle
Output Clock Random Jitter
Output Clock Random Jitter Peaking
Clock/Data Alignment: (See Figure 2.)
STM-1
STM-4
Jitter Tolerance/Jitter Transfer
* For 1 x 10
–10
BER with an optical input using 2
23
– 1 PRBS.
† Typical rise and fall time is 360 ps.
Symbol
P
I
P
MAX
LST
D
LST
I
HYS
I
CCR
V
OL
V
OH
t
R
/t
F
V
OL
V
OH
DC
J
C
J
P
TCDA
Min
—
–8
–45
–45
0.5
—
V
CC
– 1.81
V
CC
– 1.025
300
0.0
2.4
45
—
—
–800
–200
Max
–28
—
–29.0
–28.5
—
200
V
CC
– 1.62
V
CC
– 0.88
500
0.8
V
CC
55
0.01
0.1
800
200
Unit
dBm
dBm
dBm
dBm
dB
mA
V
V
ps
V
V
%
UI
dB
ns
ns
Telcordia Technologies
®
GR-253-Core and
ITU-TG.958 Compliant
DATA
OUT
50%
CLOCK
OUT
50%
T
CDA
1-725(F).b
Figure 2. Clock/Data Alignment
Agere Systems Inc.
5
AGERE [ AGERE SYSTEMS ]
