Table 12. Serial Port Timing
PARAMETER MINIMUM
SYMBOL
MAXIMUM
UNIT
2
Serial port clock period (BRR > 8002H)
6 TOSC typical
ns
tXLXL
1
Serial port clock falling edge to rising edge
(BRR > 8002H)
4 TOSC -50
4 TOSC +50
ns
tXLXH
2
Serial port clock period (BRR = 8001H)
4 TOSC typical
ns
ns
tXLXL
1
Serial port clock falling edge to rising edge
(BRR = 8001H)
2 TOSC -50
2 TOSC +50
tXLXH
1
Output data valid to clock rising edge
Output data hold after clock rising edge
Next output data valid after clock rising edge
Input data setup to clock rising edge
Input data hold after clock rising edge
Last clock rising to output float
2 TOSC -50
2 TOSC -50
ns
ns
ns
ns
ns
ns
tQVXH
1
tXHQX
1
2 TOSC +50
tXHQV
1
TOSC +50
0
tDVXH
1
tXHDX
1
2 TOSC -10
2 TOSC +10
tXHQZ
Note:
1.Tested only at initial qualification, and after any design or process changes which may affect this characteristic.
2. These specs are verified using functional vectors (strobed) only.
TXLXL
TXD
tQVXH
tXLXH
tXHQX
tXHQV
tXHQZ
RXD (OUT)
RXD (IN)
0
1
2
3
4
5
6
7
tDVXH
1
0
2
3
4
5
6
7
tXHDX
Figure 12. Serial Port Waveform - Shift Register Mode
35
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
