7
System Interface Parameters
133MHz
150MHz
Parameter
Symbol
Test Conditions
Units
M in
TBD
TBD
1.0
Max
TBD
TBD
8.0
M in
Max
TBD
TBD
8.0
8
TBD
TBD
1.0
ns
ns
ns
ns
ns
ns
Data Output
mode14...13 = 10 (fastest)
mode14...13 = 11
t
DO
mode14...13 = 00
TBD
4.0
TBD
TBD
4.0
TBD
mode14...13 = 01 (slowest)
t
t
Data Setup
t
t
= 5ns
= 5ns
DS
RISE
0
0
Data Hold
DH
FALL
Notes:
7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal.
8. Capacitive load for all output timing is 50pF.
Boot Time Interface Parameters
133/150MHz
Parameter
Symbol
Test Conditions
Units
M in
Max
t
4
0
SysClock cycles
SysClock cycles
Mode Data Setup
Mode Data Hold
DS
t
DH
5
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
Aeroflex Circuit Technology