PINOUTS
POWER TABLE
1
Port B
5 Volts
Port A
3.3 Volts
5 Volts
3.3 Volts
V
SS
3.3V or 5V
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port B Cold Spare
48-Lead Flatpack
Top View
DIR1
1B1
1B2
V
SS
1B3
1B4
VDD1
1B5
1B6
V
SS
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
V
SS
2B7
2B8
DIR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE1
1A1
1A2
V
SS
1A3
1A4
VDD2
1A5
1A6
V
SS
1A7
1A8
2A1
2A2
V
SS
2A3
2A4
VDD2
2A5
2A6
V
SS
2A7
2A8
O E2
5 Volts
3.3 Volts
V
SS
V
SS
NOTE:
1. V
DD2
cannot be tied to V
SS
while power is applied to V
D D 1
.
Control signals DIRx and OEx are 5 volt tolerant inputs. When
V
DD2
is at 3.3 volts, either 3.3 or 5 volt CMOS logic levels can
be applied to all control inputs. For proper operation connect
power to all V
DD
and ground all V
SS
pins (i.e., no floating V
DD
or V
SS
input pins). Tie unused inputs to V
SS
. If V
DD1
and
V
DD2
are not powered up together, then V
DD2
should be pow-
ered up first for proper control of OE and DIR. Until V
DD2
reaches 2.75V + 5%, control of the outputs by OE and DIR can-
not be guaranteed. During operation of the part, after power up,
insure V
DD1
> V
DD2
. Tie unused inputs to V
SS
.
2
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
