Legend for I/O fields:
TDI
= TTL compatible input
(internally pulled low)
TO
TI
CI
= TTL compatible output
= TTL compatible input
= CMOS only input
TB
TUQ
= TTL compatible bidirectional
= TTL compatible quasi-bidirectional
(internally pulled high)
TUO
= TTL compatible output
(internally pulled high)
= TTL compatible output
(internally pulled low)
= TTL compatible input
(internally pulled high)
TUB
= TTL compatible bidirectional
(internally pulled high)
TDO
TUI
TUBS = TTL compatible bidirectional Schmitt
Trigger (internally pulled high)
PWR
= +5V (VDD
)
GND
= OV (VSS
)
Table 10: 68-lead Flat Pack Pin Descriptions
QFP Pin#
I/O
Name
Active
Description
1
PWR
VDD
---
Digital supply voltage (+5V). There are 2 VDD pins, both of
which must be connected.
ECB51
NMI
2
TB
---
EDAC Check Bit 5. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 5 through pin 2 of the UT80CRH196KD.
3
4
TDI
High
Non-Maskable Interrupt. A positive transition causes a vector
through the NMI interrupt at location 203Eh. Assert NMI for at
least 1 state time to guarantee acknowledgment by the interrupt
controller.
TI
P0.3
---
---
Port 0 Pin 3. An input only port pin that is read at location 0Eh
in HWindow 0.
ECB41
TB
EDAC Check Bit 4. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 4 through pin 4 of the UT80CRH196KD.
5
6
TI
P0.1
---
---
Port 0 Pin 1. An input only port pin that is read at location 0Eh
in HWindow 0.
ECB31
TB
EDAC Check Bit 3. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 3 through pin 5 of the UT80CRH196KD.
TI
P0.0
---
---
Port 0 Pin 0. An input only port pin that is read at location 0Eh
in HWindow 0.
ECB21
TB
EDAC Check Bit 2. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 2 through pin 6 of the UT80CRH196KD.
13
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
