8 BYTES
F8
F0
INDIRECT
ACCESS
ONLY
FF
F7
•
•
•
88
80
78
70
•
•
•
8F
87
7F
77
SCRATCH
PAD AREA
•
•
•
38
DIRECT OR
INDIRECT
ACCESS
30
28
20
18
10
08
00
•
•
•
3F
37
2F
27
1F
17
0F
07
REGISTER
BANKS
BIT
ADDRESSABLE
SEGMENT
Figure 3. Internal Data Memory Organization
2.1.3 Reset
The reset input is the RST pin. To reset, hold the RST pin high
for a minimum of 24 oscillator periods while the oscillator is
running. The CPU generates an internal reset from the external
signal. The port pins are driven to the reset state as soon as a valid
high is detected on the RST pin.
While RST is high, PSEN and the port pins are pulled high; ALE
is pulled low. All SFRs are reset to their reset values as shown
in table 3. The internal Data Memory content is indeterminate.
The processor will begin operation one machine cycle after the
RST line is brought low. A memory access occurs immediately
after the RST line is brought low, but the data is not brought into
the processor. The memory access repeats on the next machine
cycle and actual processing begins at that time.
5
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
