OP295/OP495
(@ V = ±15.0 V, T = +25؇C unless otherwise noted)
S
A
ELECTRICAL CHARACTERISTICS
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
IB
30
7
300
800
20
30
±3
µV
µV
nA
nA
–40°C ≤ T A ≤ +125°C
VCM = 0 V
VCM = 0 V, –40°C ≤ T A ≤ +125°C
VCM = 0 V
Input Bias Current
Input Offset Current
IOS
±1
nA
VCM = 0 V, –40°C ≤ T A ≤ +125°C
±5
nA
Input Voltage Range
VCM
CMRR
AVO
–15
90
1000
+13.5
V
dB
V/mV
µV/°C
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
–15.0 V ≤ VCM ≤ +13.5 V, –40°C ≤ TA ≤ +125°C
RL = 10 kΩ
110
4000
1
∆VOS/∆T
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
VOL
IOUT
RL = 100 kΩ to GND
RL = 10 kΩ to GND
RL = 100 kΩ to GND
RL = 10 kΩ to GND
14.95
14.80
V
V
V
V
Output Voltage Swing Low
Output Current
–14.95
–14.85
±15
±25
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = ±1.5 V to ±15 V
90
85
110
dB
dB
VS = ±1.5 V to ±15 V, –40°C ≤ TA ≤ +125°C
VO = 0 V, RL = ∞, VS = ±18 V,
–40°C ≤ T A ≤ +125°C
Supply Current
175
µA
Supply Voltage Range
VS
+3 (±1.5)
+36 (±18)
V
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
θO
RL = 10 kΩ
0.03
85
83
V/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
0.1 Hz to 10 Hz
f =1 kHz
1.25
45
µV p-p
nV/√Hz
Current Noise Density
in
f = 1 kHz
<0.1
pA/√Hz
Specifications subject to change without notice.
(@ V = +5.0 V, V = 2.5 V, T = +25؇C unless otherwise noted)
WAFER TEST LIMITS
P aram eter
S
CM
A
Sym bol
Conditions
Lim it
Units
Offset Voltage
Input Bias Current
Vos
IB
IOS
VCM
CMRR
PSRR
AVO
VOH
ISY
300
20
±2
0 to +4
90
90
1000
4.9
150
µV max
nA max
nA max
V min
dB min
µV/V
V/mV min
V min
µA max
Input Offset Current
Input Voltage Range1
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing High
Supply Current Per Amplifier
0 V ≤ VCM ≤ 4 V
±1.5 V ≤ VS ≤ ±15 V
RL = 10 kΩ
RL = 10 kΩ
VOUT = 2.5 V, RL = ∞
NOT ES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1Guaranteed by CMRR test.
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
Model
OP295GP
OP295GS
OP295GBC +25°C
–40°C to +125°C 8-Pin Plastic DIP N-8
–40°C to +125°C 8-Pin SOIC SO-8
OP495GP
OP495GS
OP495GBC +25°C
–40°C to +125°C 14-Pin Plastic DIP N-14
–40°C to +125°C 16-Pin SOL R-16
DICE
DICE
REV. B
–3–
ADI [ ADI ]
