AD7366/AD7367
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D
V
A
1
2
24 DGND
OUT
23
22
D
B
DRIVE
OUT
BUSY
DV
CC
3
AD7366/
AD7367
4
21 CNVST
20 SCLK
19 CS
RANGE1
RANGE0
ADDR
5
TOP VIEW
6
(Not to Scale)
AGND
7
18 REFSEL
17 AGND
AV
CC
8
D
A
D
B
CAP
16
15
14
13
9
CAP
V
10
11
12
V
SS
DD
V
V
V
A1
A2
B1
B2
V
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 23
DOUTA, DOUT
B
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366 while 14
SCLK cycle are required for the AD7367. The data simultaneously appears on both pins from the simultaneous
conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366 and 14 bits
for the AD7367 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366 or 14 SCLK
cycles for the AD7367, on either DOUTA or DOUTB, the data from the other ADC follows on that DOUT pin. This
allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or
D
OUTB using only one serial port. See the Serial Interface section for more information.
2
3
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different to
the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V. To achieve a throughput rate
of 1.12 MSPS for the AD7366 or 1 MSPS for the AD7367, VDRIVE must be greater than or equal to 4.75 V.
Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential.
For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the
voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled
to DGND. Place 10 μF and 100 nF decoupling capacitors on the DVCC pin.
DVCC
4, 5
6
RANGE1,
RANGE0
ADDR
Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog
input channels. See the Analog Inputs section and Table 8 for details.
Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted,
either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic state on this pin is
latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
7, 17
8
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7366/AD7367. All analog input signals
and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages
should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be
shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient
basis. This supply should be decoupled to AGND. Place 10 μF and 100 nF decoupling capacitors on the AVCC pin.
AVCC
9, 16
10
DCAPA, DCAP
B
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer
for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on
these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied
externally to the rest of a system.
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure
of the AD7366/AD7367. The supply must be less than a maximum voltage of −11.5 V for all input ranges. See
Table 7 for further details. Place 10 μF and 100 nF decoupling capacitors on the VSS pin.
VSS
11, 12
13, 14
15
VA1, VA2
VB2, VB1
VDD
Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels
is determined by the RANGE0 and RANGE1 pins.
Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels
is determined by the RANGE0 and RANGE1 pins.
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure
AD7366/AD7367. The supply must be greater than a minimum voltage of 11.5 V for all the analog input ranges.
See Table 7 for further details. Place 10 μF and 100 nF decoupling capacitors on the VDD pin.
Rev. 0 | Page 9 of 28
ADI [ ADI ]
