AD7366/AD7367
TIMING SPECIFICATIONS
AꢁCC = DꢁCC = 4.7± ꢁ to ±.2± ꢁ, ꢁDD = 11.± ꢁ to 16.± ꢁ, ꢁSS = −16.± ꢁ to −11.± ꢁ, ꢁDRIꢁE = 2.7 ꢁ to ±.2± ꢁ, TA = TMIN to TMAX, unless
otherwise noted.1
Table 4.
Limit at TMIN, TMAX
Parameter
Unit
Test Conditions/Comments
2.7 V ≤ VDRIVE < 4.75 V 4.75 V ≤ VDRIVE ≤ 5.25 V
tCONVERT
Conversion time, internal clock. CONVST falling edge to
BUSY falling edge
680
610
10
35
30
680
610
10
48
30
ns max
ns max
kHz min
MHz max
ns min
For the AD7367
For the AD7366
Frequency of serial read clock
fSCLK
tQUIET
Minimum quiet time required between the end of serial
read and the start of the next conversion
t1
t2
t3
10
40
0
10
40
0
ns min
ns min
ns min
Minimum CONVST low pulse
CONVST falling edge to BUSY rising edge
BUSY falling edge to MSB valid once CS is low for t4 prior to
BUSY going low
t4
10
10
ns max
Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23
(DOUTB) are three-state disabled
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK low pulse width
SCLK high pulse width
2
t5
t6
t7
t8
20
7
0.3 × tSCLK
0.3 × tSCLK
10
14
7
0.3 × tSCLK
0.3 × tSCLK
10
ns max
ns min
ns min
ns min
ns max
ꢀs
t9
CS rising edge to DOUTA, DOUTB, high impedance
tPOWER-UP
70
70
Power up time from shutdown mode; time required
between CONVST rising edge and CONVST falling edge
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section and Figure 25.
2 The time required for the output to cross is 0.4 V or 2.4 V.
Rev. 0 | Page 7 of 28
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