Data Sheet
SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications T
MIN
to T
MAX
(−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
SUPPLY VOLTAGES
V
DD
V
DD_IO
PV
DD
V
AA
POWER SUPPLY REJECTION RATIO
ADV7390/ADV7391/ADV7392/ADV7393
Min
1.71
1.71
1.71
2.6
Typ
1.8
3.3
1.8
3.3
0.002
Max
1.89
3.63
1.89
3.465
Unit
V
V
V
V
%/%
INPUT CLOCK SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V, PV
DD
= 1.71 V to 1.89 V, V
AA
= 2.6 V to 3.465 V, V
DD_IO
= 1.71 V to 3.63 V.
All specifications T
MIN
to T
MAX
(−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
f
CLKIN
Conditions
1
SD/ED
ED (at 54 MHz)
HD
Min
Typ
27
54
74.25
Max
Unit
MHz
MHz
MHz
% of one clock cycle
% of one clock cycle
±ns
CLKIN High Time, t
9
CLKIN Low Time, t
10
CLKIN Peak-to-Peak Jitter Tolerance
1
40
40
2
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
ANALOG OUTPUT SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V, PV
DD
= 1.71 V to 1.89 V, V
AA
= 2.6 V to 3.465 V, V
DD_IO
= 1.71 V to 3.63 V.
All specifications T
MIN
to T
MAX
(−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Full-Drive Output Current
Conditions
R
SET
= 510 Ω, R
L
= 37.5 Ω
All DACs enabled
R
SET
= 510 Ω, R
L
= 37.5 Ω
DAC 1 enabled only
1
R
SET
= 4.12 kΩ, R
L
= 300 Ω
DAC 1, DAC 2, DAC 3
Min
33
31.5
Typ
34.6
33.5
4.3
2.0
0
10
6
1
1.4
Max
37
37
Unit
mA
mA
mA
%
V
pF
ns
ns
Low-Drive Output Current
DAC-to-DAC Matching
Output Compliance, V
OC
Output Capacitance, C
OUT
Analog Output Delay
2
DAC Analog Output Skew
1
2
DAC 1, DAC 2, DAC 3
The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
Rev. I | Page 7 of 107
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