ADV7390/ADV7391/ADV7392/ADV7393
In Case B of Figure 71, the video output signal is reduced. The
absolute level of the sync tip and blanking level both decrease
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD,
Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double
buffering improves overall performance because modifications
to register settings are not be made during active video, but take
effect prior to the start of the active video on the next field.
The range of this feature is specified for 7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
Using Subaddress 0x33, Bit 7, double buffering can be activated
on the following ED/HD registers: ED/HD Gamma A and
Gamma B curves, and ED/HD CGMS registers.
The reset value of the control registers is 0x00, that is, nominal
DAC current is output. Table 45 is an example of how the
output current of the DACs varies for a nominal 4.33 mA
output current.
Using Subaddress 0x88, Bit 2, double buffering can be activated
on the following SD registers: SD Gamma A and Gamma B curves,
SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD closed
captioning, and SD Macrovision Bits[5:0] (Subaddress 0xE0,
Bits[5:0]).
Table 45. DAC Gain Control
DAC Current
Subaddress 0x0B (mA)
% Gain
7.5000%
7.3820%
7.3640%
...
Note
0100 0000 (0x40)
0011 1111 (0x3F)
0011 1110 (0x3E)
...
4.658
4.653
4.648
...
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 71.
...
...
...
DAC 1 to DAC 3 are controlled by Register 0x0B.
CASE A
0000 0010 (0x02)
0000 0001 (0x01)
0000 0000 (0x00)
4.43
4.38
4.33
0.0360%
0.0180%
0.0000%
Reset value,
nominal
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0B
700mV
1111 1111 (0xFF)
1111 1110 (0xFE)
...
4.25
4.23
...
−0.0180%
−0.0360%
...
...
...
...
1100 0010 (0xC2)
1100 0001 (0xC1)
1100 0000 (0xC0)
4.018
4.013
4.008
−7.3640%
−7.3820%
−7.5000%
300mV
GAMMA CORRECTION
NEGATIVE GAIN PROGRAMMED IN
Subaddress 0x44 to Subaddress 0x57 for ED/HD,
Subaddress 0xA6 to Subaddress 0xB9 for SD
CASE B
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0B
700mV
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and output
brightness level (as perceived on a CRT). It can also be applied
wherever nonlinear processing is used.
Gamma correction uses the function
SignalOUT = (SignalIN)γ
300mV
where γ = gamma correction factor.
Gamma correction is available for SD and ED/HD video. For
both variations, there are 20, 8-bit registers. They are used to
program Gamma Correction Curve A and Curve B.
Figure 71. Programmable DAC Gain—Positive and Negative Gain
In Case A of Figure 71, the video output signal is gained. The
absolute level of the sync tip and blanking level both increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
ED/HD gamma correction is enabled using Subaddress 0x35,
Bit 5. ED/HD Gamma Correction Curve A is programmed at
Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma
Correction Curve B is programmed at Subaddress 0x4E to
Subaddress 0x57.
Rev. 0 | Page 53 of 96
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