ADV7190/ADV7191
Programmable gamma correction is also available. Figure 6 shows
the response of different gamma values to a ramp signal.
300
GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
GAMMA–CORRECTED AMPLITUDE
An advanced power management circuit enables optimal control
of power consumption in normal operating modes or sleep modes.
The Output Video Frames are synchronized with the incoming
data Timing Reference Codes. Optionally, the Encoder accepts
(and can generate)
HSYNC, VSYNC,
and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in master mode.
HSO/CSO
and
VSO
TTL outputs are also available and are timed
to the analog output video.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
250
SIGNAL OUTPUTS
200
0.3
0.5
150
UT
NP
LI
A
1.5
GN
SI
100
1.8
50
The ADV7190/ADV7191 also incorporates WSS and CGMS-A
data control generation and Macrovision Rev 7.1.
The ADV7190/ADV7191 modes are set up over a 2-wire
serial bidirectional port (I
2
C-compatible) with two slave
addresses, and the device is register-compatible with the
ADV7172/ADV7173.
The ADV7190ADV7191 is packaged in a 64-lead LQFP
package.
DATA PATH DESCRIPTION
0
0
50
100
150
LOCATION
200
250
Figure 6. Signal Input (Ramp) and Selectable Gamma
Output Curves
The on-board SSAF (Super Subalias Filter) with extended
luminance frequency response and sharp stopband attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness
control feature allows high-frequency enhancement on the lumi-
nance signal.
The device is driven by a 27 MHz clock. Data can be output at
27 MHz or 54 MHz (on-board PLL) when 4 oversampling is
enabled. Also, the output filter requirements in 4 oversampling
and 2 oversampling differ, as can be seen in Figure 7.
0dB
2 FILTER
REQUIREMENTS
4 FILTER
REQUIREMENTS
For PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656/601-compatible Pixel
Port at a 27 MHz data rate. The pixel data is demultiplexed to
form three data paths. Y typically has a range of 16 to 235, Cr
and Cb typically have a range of 128+/–112; however, it is
possible to input data from 1 to 254 on both Y, Cb, and Cr.
The ADV7190/ADV7191 supports PAL (B, D, G, H, I, N, M)
and NTSC M, N (with and without Pedestal) and PAL60 stan-
dards. Digital Noise Reduction can be applied to the Y signal.
Programmable gamma correction can also be applied to the Y
signal if required.
The Y data can be manipulated for contrast control and a set-up
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next field when double buffering is
enabled.
The appropriate sync, blank, and burst levels are added to the
YCrCb data. Macrovision antitaping, (ADV7190 only) Closed-
Captioning, and Teletext levels are also added to Y and the
resultant data is interpolated to 54 MHz when 4× Oversampling
is enabled. The interpolated data is filtered and scaled by three
digital FIR filters.
The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are added together to make up
the Chrominance Signal. The Luma (Y) signal can be delayed
by up to six clock cycles (at 27 MHz) and the Chroma signal
can be delayed by up to eight clock cycles (at 27 MHz). The
Luma and Chroma Signals are added together to make up the
Composite Video Signal. All timing signals are controlled.
The YCrCb data is also used to generate RGB data with appropri-
ate sync and blank levels. The YUV levels are scaled to output
the suitable SMPTE/EBU N10, MII, or Betacam levels.
–30dB
6.75MHz
13.5MHz
27.0MHz
40.5MHz
54.0MHz
Figure 7. Output Filter Requirements in 4
×
Oversampling
Mode
ADV7190/ADV7191
2
6
I
N
T
E
R
P
O
L
A
T
I
O
N
D
A
C
O
U
T
P
U
T
S
54MHz
OUTPUT
RATE
MPEG2
PIXEL BUS
27MHz
ENCODER
CORE
54MHz
PLL
Figure 8. PLL and 4
×
Oversampling Block Diagram
The ADV7190/ADV7191 also supports both PAL and NTSC
square pixel operation. In this case the encoder requires a
24.5454 MHz Clock for NTSC or 29.5 MHz Clock for PAL
square pixel mode operation. All internal timing is generated
on-chip.
–12–
REV. 0
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