ADV7180
Bits (Shading Indicates Default
State)
Comments
LQFP-64 LFCSP-40
Subaddress Register
Bit Description
Notes
7
6
5
4
3
2
1
0
0
1
0x07
Autodetect Enable
AD_PAL_EN. PAL B/G/I/H
autodetect enable.
Disable
Enable
Disable
AD_NTSC_EN. NTSC
autodetect enable.
0
1
Enable
Disable
AD_PALM_EN. PAL M
autodetect enable.
0
1
Enable
Disable
AD_PALN_EN. PAL N
autodetect enable.
0
1
Enable
Disable
AD_P60_EN. PAL 60
autodetect enable.
0
1
Enable
Disable
AD_N443_EN.
NTSC 4.43 autodetect
enable.
0
1
Enable
Disable
AD_SECAM_EN. SECAM
autodetect enable.
0
1
Enable
Disable
AD_SEC525_EN.
SECAM 525 autodetect
enable.
0
1
1
Enable
0x08
Contrast Register
CON[7:0]. Contrast
adjust. This is the user
control for contrast
adjustment.
0
0
0
0
0
0
0
Luma gain = 1
0x00 gain = 0,
0x80 gain = 1,
0xFF gain = 2
0x09
0x0A
Reserved
Reserved.
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Brightness Register
BRI[7:0]. This register
controls the brightness
of the video signal.
0x00 = 0IRE,
0x7F = +100IRE,
0x80 = –100IRE
0x0B
0x0C
Hue Register
HUE[7:0].
0
0
0
0
0
0
0
0
Hue range = −90° to +90°
This register contains
the value for the color
hue adjustment.
Default Value Y
DEF_VAL_EN. Default
value enable.
0
1
Free-run mode dependent
on DEF_VAL_AUTO_EN
Force free-run mode on
and output blue screen
DEF_VAL_AUTO_EN.
Default value.
0
1
Disable free-run mode
When lock is lost, free-run
mode can be enabled to
output stable timing, clock,
and a set color
Enable automatic free-run
mode (blue screen)
DEF_Y[5:0]. Default
value Y. This register
holds the Y default
value.
0
0
0
1
1
1
1
1
0
0
1
0
1
1
0
Y[7:0] = {DEF_Y[5:0], 0, 0}
Default Y value output in
free-run mode
0x0D
0x0E
Default Value C
ADI Control
DEF_C[7:0]. Default
value C. The Cr and Cb
default values are
0
0
0
0
Cr[7:0] = DEF_C[7:4], 0, 0, 0, 0}
Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0}
Default Cb/Cr value output
in free-run mode; default
values give blue screen
output
defined in this register.
Reserved.
Set as default
SUB_USR_EN. Enables
user to access the
interrupt/VDP register
map.
0
1
Access main register space
See Figure 50
Access interrupt/VDP register
space
Reserved.
0
0
Set as default
Rev. A | Page 82 of 112
ADI [ ADI ]
